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PCIe 7.0 Specification v0.5 Published - Full Spec Next Year

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  • PCIe 7.0 Specification v0.5 Published - Full Spec Next Year

    Phoronix: PCIe 7.0 Specification v0.5 Published - Full Spec Next Year

    The PCI-SIG announced today that they have published their newest revision "version 0.5" of the forthcoming PCI Express 7.0 specification...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    What's this? Pulling a USB?

    Why not "7.0 Beta" or something like that?

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    • #3
      Still it's better than PCIe 6.1 gen 2 16x16 V202404.5

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      • #4
        Originally posted by sobrus View Post
        Still it's better than PCIe 6.1 gen 2 16x16 V202404.5
        This isn't version 0.5 of PCIe 7. It's 0.5 version of the specification for it.. not sure why semver is suddenly frowned upon, since that's what people usually want...

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        • #5
          I was planning to wait for Zen 5 or Arrow Lake for my next desktop upgrade, but I got antsy and just built an AM5 / Zen 4 system over the weekend. Last I had read, PCIe 6.0 devices would start shipping sometime in 2024. The bandwidth gains are awesome, but I wish we'd get more sane / useful layouts on consumer devices. E.g. my new motherboard has an x16 PCIe 5.0 slot which sounds nice for future proofing. But I would much rather the equivalent bandwidth from that one slot be delivered by PCIe 4.0 x16 / x8 / x4 / x4 slots.

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          • #6
            Crazy how 7.0 x1 is faster than 3.0 x16, when you consider 3.0 is still quite good in most cases.

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            • #7
              The SI issues for PCIe Gen 7 is going to require PCB vendors to shorten traces and add even more layers. It is going to be quite the expensive board (although the server space is not as price sensitive as the consumer market).

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              • #8
                Originally posted by CommunityMember View Post
                The SI issues for PCIe Gen 7 is going to require PCB vendors to shorten traces and add even more layers. It is going to be quite the expensive board (although the server space is not as price sensitive as the consumer market).
                That is why they went to PAM4 encoding. More bits with less frequency, trying to mitigate the high speed signaling issues.

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                • #9
                  [ they prepared mostly always 2 gens of development milestones in advance for display, what makes me curious, what v8.0 and v9.0 (~TB each direction for x16, ~60GB/(s*x1) could keep on doubling bandwidth (PCIe 3.0 ~0.985GB/(s*x1), PCIe 4.0 ~1.97GB/(s*x1), PCIe 7.0 ~15.1GB/(s*x1) each direction lane ) and staying compatible through all versions and 'FEW' (forward error correction) since 6.0; with enabling doubling bw development, they would definitely 'brake records' for bw on consumer devices (for an arriving decade's scale), maybe only challenged by Thunderbolt&USB (~10GB/s(-120Gbps_unidir)_2024)? ]
                  Last edited by back2未來; 02 April 2024, 11:33 PM. Reason: adding details

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                  • #10
                    Originally posted by pWe00Iri3e7Z9lHOX2Qx View Post
                    I was planning to wait for Zen 5 or Arrow Lake for my next desktop upgrade, but I got antsy and just built an AM5 / Zen 4 system over the weekend. Last I had read, PCIe 6.0 devices would start shipping sometime in 2024. The bandwidth gains are awesome, but I wish we'd get more sane / useful layouts on consumer devices. E.g. my new motherboard has an x16 PCIe 5.0 slot which sounds nice for future proofing. But I would much rather the equivalent bandwidth from that one slot be delivered by PCIe 4.0 x16 / x8 / x4 / x4 slots.
                    Yeah the whole PC platform "architecture" is royally screwed up.

                    The apparent model is that a basic PC with CPU+IGPU should be enough for "most anyone" so expansion capability is almost neglected entirely in practice other than by plugging in random slower USB2/3 stuff.

                    Then for the "gamers" or "productivity" people, ok, buy a premium motherboard and we'll give you one decent PCIE x16 slot where you can install one GPU and probably have things sort of work mechanically / thermally / electrically.

                    Oh, you want more M.2 SSDs, 2-4 GPUs, maybe a couple 10-100 Gb NICs? Several high capability TB / USB4 / type C ports? Too bad for you, you're not getting anywhere near enough PCIE lanes / slots / USBC ports / USB4 ports etc. to basically get away with more than a couple significant peripherals. Maybe if you buy the halo $1200 motherboard you can have another usable slot or two for PCIE.

                    So USB4 / newer thunderbolt, newer PCIE4/5/+ are all very nifty things. So is ECC DRAM etc. etc. M.2 NVME SSDs. I'm looking forward to the day when I can actually USE a non-trivial amount (1-2) of such things in a reasonable "prosumer" computer.

                    But as the NVIDIA 4090 shows basically the GPU's already just about the size of many motherboards so even if you HAD the slots for more,
                    you're not going to have the space mechanically or PSU / cable sanity if you tried.

                    Can't we just make PCs scalable again? I remember "easily" being able to get 6-8 ISA or PCI slots on motherboards for modest cost.
                    Dual-socket ones also.

                    Now the back panel is such a cluster you can't even really see or have room to plug in adjacent USB etc. ports.

                    How's this going to work for the next 3-4 desktop PC generations?

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