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Linux Patches Updated For 64-Core RISC-V Milk-V Pioneer mATX Board

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  • Linux Patches Updated For 64-Core RISC-V Milk-V Pioneer mATX Board

    Phoronix: Linux Patches Updated For 64-Core RISC-V Milk-V Pioneer mATX Board

    The latest Linux kernel patches for enabling the Milk-V Pioneer board have been posted, which is that interesting 64-core RISC-V micro-ATX board with two PCIe x16 slots and more...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    "Milk-V"

    What's with Asian marketers and their complete and utter inability to name shit without sounding like freakshows??

    This has been going on since forever; the Japanese couldn't even advertise "House Curry" when I was growing up there in the 70's without revealing their cultural obliviousness.

    (Apologies; my gripe isn't Linux-related. It's been a 40+ year pet peeve.)

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    • #3
      The current machines are limited to distro maintainers for building and testing packages, using a vendor-provided kernel, of course. Some package maintainers have already received the Milk-V. However, the software ecosystems are not yet 'benchmarking ready.' Even basic toolchains are failing at build time, and I highly doubt how many parts of the Phoronix test suite could run successfully without encountering a crash. We are experiencing lots of SIGSEGV: invalid memory references on HiFive Unmatched when compiling with Rust. Additionally, there are many segfaults on SG2042 with node v8 JIT, essentially blocking the build of popular packages like Chromium (which requires Node.js to build). Even when using qemu as build machine as a "safe fallback", you will encounter a lot of segfaults randomly in both system mode and user mode. Moreover, if you attempt a Rust build on qemu-user, you have a good chance of encountering a deadlock. If you enable LTO, your memory is probably not sufficient for qemu-user to perform LTO (it requires more than 16GB at times).

      By the way, there is another quirk with this specific processor core in the SG2042 or the T-Head XuanTie series core. All C906/C910/C920 processors cannot pass glibc's IEEE-754 tests because the FPU in these CPU cores does not generate underflow float exceptions, which is not compatible with the IEEE-754 standard and is even a direct violation of the RISC-V ISA. The ISA requires the CPU cores to be IEEE-754 compliant. The RISC-V ISA even enforces that the core should detect tininess after rounding, but the C910's FPU does allow for the detection of tininess before rounding. So, the fastest RISC-V CPU that money can buy at the moment actually breaks the RISC-V ISA and requires very special handling. I know it is a very basic requirement for a processor with an FPU: to be IEEE-754 compliant, but our dear implementers have their own ideas about how it should be handled.
      Last edited by gnattu; 06 October 2023, 12:49 AM.

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      • #4
        There's a github repo that's been put up to accept Issues with this RISC-V board. https://github.com/milkv-pioneer/issues/issues

        From reading through the issues (all written in Chinese), it appears that Fedora 38 has been gotten to run on the board.

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        • #5
          We are slowly moving into teritory where it is viable to use these chips for cloud-native datacenter workloads.
          Good to see healthy competition on that front.

          Toolchains are coming together as well and more and more libraries are starting / are getting optimized for RISC-V. The vector Extensions are quite Unique in RISC-V as they are made, such that one generic code path can use hardware targets with different widths, which is quite cool, but different from other approaches.
          The Xuantie Cores (C9xx) only implement the now deprecated 0.7 standard of the Vector extensions.

          Guess these many-cores designs we see know could be a game changer, as they are quite efficient + cheap.

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          • #6
            Prices are still shit though. $1.500 for a board with SoC.
            Yikes.

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            • #7
              The v4 patch link should be https://lore.kernel.org/linux-riscv/[email protected]/, there are some duplicated subjects due to wrong sending.

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              • #8
                Originally posted by Brane215 View Post
                Prices are still shit though. $1.500 for a board with SoC.
                Yikes.
                Not too bad for 64 cores and ECC capability. Just wish it had 10 Gb Ethernet, not 2.5.

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                • #9
                  I had never heard of this board so thanks for bringing it to my attention. Out of my price range at the moment but feature wise is exactly what I want.

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                  • #10
                    Originally posted by unwind-protect View Post

                    Not too bad for 64 cores and ECC capability. Just wish it had 10 Gb Ethernet, not 2.5.
                    ixgbe does not work with this board due to firmware issues, don't know if other cards would work.

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