ASUS Unveils The Tinker V As Their First RISC-V Board

[coder]

I would be very interested in one of these. The only missing piece is mainstream Linux support. Sad about the lack of an open source BIOS too. Thank you for the link.

Note that it came about as a partnership with Intel, and contains some Intel IP. We therefore should neither take it for granted, nor assume there will be a successor. I think it was made primarily as an IFS demo project, as well as a software development vehicle to help bootstrap the non-embedded RISC-V software ecosystem.

"The SoC integrates Intel’s own PCIe 5.0 PHY with x8 lanes along with Synopsys PCIe 5 Controller. It also integrates Intel’s DDR5 PHYs supporting 5600 MT/s rates along with Cadence’s memory controller. Other Intel’s own Intel 4 IPs include 2 MiB of shared SRAM (part of their memory compiler), process monitor, caches, Power/Clock/PLLs, electronic fuses, JTAG, and various cell libraries."

Source: https://fuse.wikichip.org/news/7277/...tel-4-process/

[ezst036]

SiFive have been working toward this for some time. They've announced a microATX board called the HiFive Pro P550. (Edit: But I guess they don't support coreboot.)

https://www.sifive.com/boards/hifive-pro-p550

I would be very interested in one of these. The only missing piece is mainstream Linux support. Sad about the lack of an open source BIOS too. Thank you for the link.

[jacob]

POWER10 systems currently require non-free blobs to initialise the modular memory. Not everyone is happy with this. The hope of some is that RISC-V will enable the production of 'blob-free' systems, which is important to some people.

Phoronix: Binary Blobs Continue To Prove Challenging For POWER10 Plus Very Expensive Motherboards

Maybe there is something that I'm not aware of, but it seems to me that RISC-V is no more likely to bring a fully FOSS, blob-free architecture than ARM or x86. Just because the ISA is royalty free doesn't mean manufacturers won't sell chips with proprietary microcode and management engines just like everyone else - in fact, it may even make it easier for them licence-wise. The free ISA was a promise of a more lively ecosystem but honestly even that doesn't really seem to be happening, unless you count ultra low end mobile SoCs at $1000 a pop.

[stiiixy]

POWER10 systems currently require non-free blobs to initialise the modular memory. Not everyone is happy with this. The hope of some is that RISC-V will enable the production of 'blob-free' systems, which is important to some people.

Phoronix: Binary Blobs Continue To Prove Challenging For POWER10 Plus Very Expensive Motherboards

"Apparently" P11 wont have the unfortunate set-back that P10 suffers from. If you read the supporting links from the Phoronix posts, especially from the chap who made the case, you'd know.

P11, however, has a release date of "in the future" as far as I'm aware.

[macemoneta]

It would be interesting to know how the GbE ports are connected. Are they USB like on Raspberry Pi?

The Raspberry Pi 4, unlike previous models, does not have a USB-based Ethernet; It's driven direct by the CPU with a PHY:

https://heise.cloudimg.io/width/712/...db4be588cf.png

[Old Grouch]

It could be an interesting target for OpenWrt - with two GigE ports, one faces the WAN, and the other a local switch. Given the cpu specifications, I doubt it could route a full GigE of traffic, but it would be nice to get more RISC-V options for OpenWrt.

The specifications say it has 1 x microUSB and 1 x microUSB OTG.

For OpenWrt use, the CAN Bus is superfluous, not so sure about the RS232

Just to be clear, OpenWrt support for a (different) RISC-V SOC already exists. So it's 'just' a potential additional option.

[Old Grouch]

A fully open source friendly architecture with ATX boards and most importantly competitive performance already exists in the form of POWER9/10. I'm not sure what would RISC-V bring to the table that POWER doesn't offer already.

POWER10 systems currently require non-free blobs to initialise the modular memory. Not everyone is happy with this. The hope of some is that RISC-V will enable the production of 'blob-free' systems, which is important to some people.

Phoronix: Binary Blobs Continue To Prove Challenging For POWER10 Plus Very Expensive Motherboards

[Old Grouch]

Unfortunately the SoC on this board violates the RISC-V privileged spec with its address translation (see https://lore.kernel.org/all/CA++6G0D...ail.gmail.com/). The core has Instruction and Data Local Memory regions, with virtual address ranges that match the ranges chosen for the memory regions (baked into the hardware) bypassing normal translation, not physical addresses (which would be completely legal). Supporting this therefore requires the OS to have special handling to know that parts of the virtual address space can never be allocated, which is not a normal thing, and a bit intrusive. Moreover, these virtual address ranges overlap the default base address for position dependent binaries on RISC-V (whether using GNU ld or LLVM LLD), so no position dependent binaries linked in the past however many years will work on this, instead they must be rebuilt with a different base address. It's therefore pretty dubious for them to claim that Debian is supported; not only does it need a vendor kernel (for now) as is usually the case for new Arm and RISC-V hardware, but it also requires some subset of the packages to be rebuilt with a modified toolchain or build flags.

That's...unhelpful. Goes with the territory of the RISC-V wild west, though. The discussion the linked message is embedded in is interesting. I wonder what the commercial, or other, pressures are that push manufacturers to go in such directions.

[miskol]

I did hope that ASUS will release board with RK3588.

[ayumu]

Although RISC-V might not be a technically superior ISA for server computing.

RISC-V is inferior to none.

The server chips are coming, as early as H2 this year (Ventana). Next year, there'll be several.