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Libre RISC-V Accelerator Secures 300k EUR In Grants, Still Undecided About The ISA

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  • #21
    Originally posted by programmerjake View Post

    That's true, but only if you ignore the graphics instructions we're adding. Once added, the ISA would include all the important operations from known-working GPU ISAs such as AMD GCN, so it would then be completely suitable to implement a GPU. The rest of what's needed are good drivers and good microarchitecture.

    Additional source code link:
    Ok - but to avoid a complex technical discussion, I'll just point out that modern GPUs have >4000 computation cores. So you'll be trying to build a multi-core CPU that is significantly larger than anything on the market today to get anywhere near - and *really* not be using it particularly efficiently. Or you'll have to restart with blank sheet of paper and a new instruction architecture ground up designed specifically for highly parallel, pipelined numerical calculation...


    • #22
      Originally posted by OneTimeShot View Post
      Or you'll have to restart with blank sheet of paper and a new instruction architecture ground up designed specifically for highly parallel, pipelined numerical calculation...
      Nobody starts with a blank sheet nowadays. You have libraries of function blocks, like rasterizers, texture samplers etc.

      So those graphics instruction blocks should be perfectly reusable if someone wanted to design a more performance oriented chip. That is the real value of this project imho.


      • #23
        Originally posted by pkese View Post

        There already exist a bunch of opensource RISC-V implementations:
        How about taking one of those and add the Vector extension to it?
        someone else mentioned larrabee in this thread: that and jeff bush's work on nyuzi tells you what you need to know.

        I'm trying to understand how is this different (i.e. what's the innovative contribution, besides the 'not invented here' syndrome)...
        appreciated, it's a good question. i spent 18 months prior to putting in the NLNet *first* Grant request, because i despise NIH. i have RSI: typing gets painful, therefore why would i deliberately do that, yeah??

        a fantastic high performance Vector Processor simply does not make a GPU. this is just a fact. you can have all the Vector Processing in the world, however the last bit of accuracy in FP32 (ULP) requires 4x the amount of hardware (4x the power consumption) compared to a less accurate *useable* GPU equivalent, where exact IEEE754 compliance is simply not necessary all the time.

        thus you can have a perfect Vector Engine yet compared to a GPU centric engine its power performance is completely noncompetitive.

        in addition, certain types of 3D computation simply do not fit well into "standard" Vector operations. Jeff Bush illustrates several in his Nyuzi paper.

        basically, 3D GPU is a whole new level above a plain Vector Engine, hence we have *not* gone mad and deluded ourselves that we are reinventing second hand wheels.

        it would be great to use pulpino however unfortunately they tied their work too closely to the RISCV Vector Extension to be able to do so.


        • #24
          Originally posted by Michael View Post

          Their current plan is focused on Kazan for Vulkan, but LLVMpipe theoretiically would work too.

          Keep in mind they are setting very low performance expectations (~25 FPS at 720p) compared to Intel and other efforts aiming for legitimately high performance.
          keep in mind that there has been a ramp-up curve here spanning nearly 40 years. also that you are referring to companies that do full custom ASICS, which cost USD 100 million to design.

          yes, without realising it, you are saying, "why are these people not doing a full custom ASIC as their very first chip, why have they not gone for VC funding of over half a billion dollars so they can do a few iterations of full custom ASICs?"


          walk before run.

          therefore we will be doing a 180nm chip first. this is a sponsored tapeout that will only cost USD 600 per square millimetre. we need around 40 square millimetres.

          where normally a chip would be half a million, one million, two million just for the mask charges, we do not have those, just the production costs in a 180nm shuttle service.

          once we have iterated at that level, we can move up to the next level (45nm quad core).

          once we have iterated at that level, we can move up again with VC funding to 1000 cores and 7nm and so on.

          this is just a responsible way to do things.


          • #25
            some nice news btw, will leave the phoronix team to decide if they want to pick it up soon, the OpenPower Foundation released their EULA which was what we were waiting on. it looks really good, very well designed.