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Libre RISC-V Accelerator Secures 300k EUR In Grants, Still Undecided About The ISA

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  • #11
    Originally posted by pkese
    There already exist a bunch of opensource RISC-V implementations: https://github.com/riscv/riscv-cores-list How about taking one of those and add the Vector extension to it?
    According to lkcl in a previous phoronix thread, many of those require proprietary compilers, and the remaining ones were made in some hard to work with custom language. This project would be usable entirely with FOSS.

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    • #12
      Originally posted by curaga View Post
      According to lkcl in a previous phoronix thread, many of those require proprietary compilers, and the remaining ones were made in some hard to work with custom language. This project would be usable entirely with FOSS.
      For those following from home, the high-complexity modern electronic integrated circuits aren't designed graphically like you would design a printed circuit board with traces and stuff.
      You literally have billions of logic gates all over the place, it's not practical in the slightest.

      You "write" the integrated circuit design in "electronics design code" (Hardware Description Language, HDL) which is then read and "compiled" by a compiler software into a phyisical design that the fab can manufacture.
      Examples of such languages would be Verilog and VHDL.

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      • #13
        Originally posted by bachchain View Post
        I can definitely see how, for a project called "Libre RISC-V", the ISA is a point of debate.
        </s>
        Especially when they've received a bunch of grants, under that name.

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        • #14
          Wow - from what I've seen of the Libre RISC-V GPU project (which isn't much - they haven't even picked POWER or RISC-V) this is going to be money down the drain.

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          • #15
            Originally posted by bachchain View Post
            I can definitely see how, for a project called "Libre RISC-V", the ISA is a point of debate.
            </s>
            Originally posted by microcode View Post

            Especially when they've received a bunch of grants, under that name.
            We're planning on having the GPU be able to run RISC-V code even if we decide to use OpenPower, it would then support at least RV64GC user mode so programs that don't use our graphics extensions would still run at full speed. This would be implemented similarly to how x86-64 Linux can still run x86-32 programs. See the thread about that: http://lists.libre-riscv.org/piperma...er/003104.html

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            • #16
              Originally posted by OneTimeShot View Post
              Wow - from what I've seen of the Libre RISC-V GPU project (which isn't much - they haven't even picked POWER or RISC-V) this is going to be money down the drain.
              A lot of the hardware and software work doesn't actually depend on which ISA we pick. For example, I'm currently working on Kazan (the Vulkan driver), writing the shader compiler code that translates from SPIR-V to LLVM IR (as well as potentially other backend compilers, such as GCC or Cranelift) and performs the required vectorization steps to translate from SIMT to variable-length vectors.
              Last edited by programmerjake; 29 December 2019, 05:59 PM. Reason: most -> a lot

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              • #17
                Originally posted by OneTimeShot View Post
                Wow - from what I've seen of the Libre RISC-V GPU project (which isn't much - they haven't even picked POWER or RISC-V) this is going to be money down the drain.
                I guess the money for the EOMA68 has finished and he needs to eat (yes it's the same guy). Not that the EOMA68 has shipped or anything.

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                • #18
                  Originally posted by starshipeleven View Post
                  I guess the money for the EOMA68 has finished and he needs to eat (yes it's the same guy). Not that the EOMA68 has shipped or anything.
                  Just to clarify, in case anyone was wondering, LKCL is part of EOMA68, however, I am not.

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                  • #19
                    Originally posted by programmerjake View Post
                    A lot of the hardware and software work doesn't actually depend on which ISA we pick.
                    That's true. Neither RISC-V nor Power architecture is sensible for a GPU implementation.

                    For everyone else, I believe that the code is here:
                    https://git.libre-riscv.org/

                    the issue tracker is here:
                    http://bugs.libre-riscv.org/

                    and the mailing list is here:
                    http://lists.libre-riscv.org/pipermail/libre-riscv-dev/

                    People can read these (it won't take long) and make up their own minds...

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                    • #20
                      Originally posted by OneTimeShot View Post

                      That's true. Neither RISC-V nor Power architecture is sensible for a GPU implementation.
                      That's true, but only if you ignore the graphics instructions we're adding. Once added, the ISA would include all the important operations from known-working GPU ISAs such as AMD GCN, so it would then be completely suitable to implement a GPU. The rest of what's needed are good drivers and good microarchitecture.

                      Additional source code link: https://salsa.debian.org/Kazan-team

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