Originally posted by Brane215
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But even then it would be nice to have somewhat parametrised test with declared wire length and capabilities etc.
It's part of existing, quite expensive eqipment that I have to work around. Telling a customer to spit a 20k to buy new gear just so I can feel modern is out of the question.
Obvious disadvantage is the need of uC. But it could be quite trivial logic on firmware side, uC guaranteed to have "proper" timers, clocked by high-speed source, IO is fast and predictable, etc. IMHO, its wrong idea to try to turn PC into uC. PC is very crappy and troublesome uC. And I doubt customer who spent 20K on device would care much about $10 for uC addon. OTOH, decreased development time and relaxed requirements on PC are likely good things to have. And I guess customer would like idea to be able to use just any arbitrary PC without hardcore special requirements. Even notebook which lacks COM ports, etc, etc.
Or writing a specialised driver within kernel, which would reserve particular COM port, make new "device" and enable access to it through IOCTLs.
1) Generally, PC may or may not have high-res timer. PCs were never meant for dealing with precise timings. Recent PCs usually have TSC, HPT and so on. But it makes assumptions about PC which may or may not be true. And it can be disabled in BIOS sometimes.
2) PCs have noteworthy jitters. Cache hit and miss are different things, etc.
3) PCs aren't great at fast GPIO, your PIC probably could do it both faster and with far more predictable and accurate timings.
4) What if there will be SMI interrupt? Neither you know how long BIOS SMI service routine going to take, nor you can prevent it on x86. SMM is most privileged mode of x86. SMI can't be masked. At very most, you can detect SMI has occured. Then its way too late to do anything about it. At most you can notice constraints were violated.
5) Other kernel parts are running and can have own ideas about timings.
I'm not sure if (relatively rare) failures to fufill what you've promised matter in this particular task (maybe this task is ok with some percent of measures which are fucked up), but generally it sounds like a poor plan to me.
So how do you use that to synchronise internal clock to something like 1?s or better ?
With ordinary COM port, it's not _that_ hard. You choose one of COM port hadshake pins that can generate an interrupt ( like RTS/CTS) and connect PPS signal to it. Then you program the HW to generate interrupt on pin change. In interrupt handler you can simply record TSC counter ( 64-bit counter with 1ns resolution)
and make it available to userland through /proc. Same userland can determine and order RTC clock change on next PPS, for example.
All in-kernel tasks are here simple, low-CPU load and done without interrupts, in one short timeslice.
Comport useage is usually intermittent ( debug, update etc) and system load then is not a problem.
On my Phenom, I can see LPT and COMon their standard port addresses. Likewise with addon PCI card and I suspect with PCIe version it would be the same.
But even if they were done through MEMIO, as long as there is direct access to the metal and open source kernel driver, it would be fine with me.
It matters to me. With such solution I can standardise my purchases and use one chip for many roles and so buy greater qty with better price per part. This means lower manufacturing prices and less hassle with mateerial purchase. And substantial savings. And less problems/costs with servicing.
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