amd is winner
No needs of calculation..i am betting to you all guys..amd six core zambezi is going to beat intel core i5 SB..performance 'll be in between i7 and i5 SB..and 8 cores means 4 modules(u all knows about amd modules) going to beat i7 SB and i7 extreme 6 cores and porformance in between 6 cores extreme i7 and upcoming i7 8 cores SB based..and upcoming BD..with little tweaks 'll beat SB..and competets untill enhanced BD 'll be out..haha..u r thinking that i m crazy amd fanboy..i am..bt thats reality..amd is back with FX..as in 2006..same for server xeon is going tn beaten by interlagos..think abut bobcat..1.6 ghz zacate is beating 1.8 ghz atom with H.T..and intel is going to compete by 32 nm oak tail..with little lead..so what abut 28 nm krishna and wachita..haha..amd is winner..and i love it..amd 'll kick intel out..ameen
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AMD Bulldozer Dual-Interlagos Benchmarks On Linux
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Originally posted by zerix01 View PostNo, Bulldozer has a flexable FPU. If C-ray is using 256 bit FP calculations then yes it appears as one FPU per two cores. But if it is using 128 bit FP's then each core has it's own FPU. Better yet if C-ray uses 64 bit FP's then each core has two FPU's.
For me personally, I am a big Folding@Home user. It can scale to 128 threads and only uses 64 bit floating point ops. Bulldozer will be amazing.
with
are probably going to serve you better , i imagine there will be a Nvidia with PCI express 3.0 bus by then too OC.
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Originally posted by bbordwell View PostI just found this out and have not seen it come up yet in discussion, C-ray measures floating point performance which is bulldozers weak point as it only has one FP unit per module. Integer performance then should be about double which would put it on par with sandy bridge.
Originally posted by Jimbo View PostIts pretty interesting what AMD has done. Just forget about the number of cores!, they created the bulldozer module which contains 2 integer cores and 1 FP core. A CPU will contain various bulldozer modules.
This redesign is aimed to increase performance on generic programs, which uses lot of integer operations (games included). Programs which makes use of a lot of FP operations (math, video encoders...) would probably not get performance boost.
Indeed, it should be interesting to see more tests of this AMD CPU redesign.
like i said above , a simple git pull, compile, and checkasm --bench result will show this and no auto vectorisation compiler mess to contend, with as at least the assembly is hand coded and yasm macro based re-processing, an/or you could always add in the x264 timing code (i think Loren <pengvado> Merritt originally wrote)
Pastebin.com is the number one paste tool since 2002. Pastebin is a website where you can store text online for a set period of time.
Code:#include <stdio.h> #include <string.h> #include <inttypes.h> static __attribute__((always_inline)) uint64_t read_time(void) { if(sizeof(long)==8) { uint64_t a, d; asm volatile( "rdtsc\n\t" : "=a" (a), "=d" (d) ); return (d << 32) | (a & 0xffffffff); } else { uint64_t l; asm volatile( "rdtsc\n\t" : "=A" (l) ); return l; } } #define NOP_CYCLES 22 // time measured by an empty timer on core i7 #define START_TIMER \ uint64_t tend;\ uint64_t tstart= read_time(); #define STOP_TIMER(id) {\ tend= read_time();\ {\ static uint64_t tsum=0;\ static int tcount=0;\ static int tskip_count=0;\ if(tskip_count<2)\ tskip_count++;\ else{\ if(tcount<2 || tend - tstart < 16*tsum/tcount + 100000){\ tsum+= tend - tstart;\ tcount++;\ }else\ tskip_count++;\ if(((tcount+tskip_count) & (tcount+tskip_count-1)) == 0)\ printf("%"PRIu64" decicycles in %s, %d runs, %d skips\n", tsum*10/tcount-NOP_CYCLES*10, id, tcount, tskip_count);\ }}} #define STOP_TIMER_SUM(id) {\ tend= read_time();\ {\ static uint64_t tsum=0;\ static uint64_t tother=0;\ static uint64_t tend0=0;\ static int tcount=0;\ tsum += tend - tstart;\ if(tcount)\ tother += tstart - tend0;\ tend0 = tend;\ tcount++;\ if((tcount & (tcount-1)) == 0 && tcount > 4)\ printf("%"PRIu64"/%"PRIu64" cycles %s, %d runs\n", tsum-NOP_CYCLES*tcount, tother+tsum-NOP_CYCLES*tcount, id, tcount);\ }}
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I meant how they are used logically not physically, in direct response to the other user saying there is only one FPU at all no matter what the type of instruction being used.
You are saying two different things here.
Originally posted by smitty3268 View PostEverything I've seen says this is wrong. Do you have a source?
Bulldozer is supposed to have 1 FP core per module, versus 2 integer cores. They say this allows them to make the FP core beefier than it would have been otherwise, because it's one of the more complicated (and therefore expensive) portions of the CPU.
Originally posted by smitty3268 View PostIt is supposed to emulate the 256 bit AVX instructions by transparently using 2 128 bit SSE registers at once, perhaps that's what confused you?
Now I could be wrong by saying thee are two separate 128 bit FPU's. But that would mean the BD architecture pictures we have seen are a logical view not a physical one. Otherwise I keep seeing two separate FPU's per module.
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Originally posted by zerix01 View PostNo, Bulldozer has a flexable FPU. If C-ray is using 256 bit FP calculations then yes it appears as one FPU per two cores. But if it is using 128 bit FP's then each core has it's own FPU. Better yet if C-ray uses 64 bit FP's then each core has two FPU's.
For me personally, I am a big Folding@Home user. It can scale to 128 threads and only uses 64 bit floating point ops. Bulldozer will be amazing.
Bulldozer is supposed to have 1 FP core per module, versus 2 integer cores. They say this allows them to make the FP core beefier than it would have been otherwise, because it's one of the more complicated (and therefore expensive) portions of the CPU.
It is supposed to emulate the 256 bit AVX instructions by transparently using 2 128 bit SSE registers at once, perhaps that's what confused you?
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Originally posted by bbordwell View PostI just found this out and have not seen it come up yet in discussion, C-ray measures floating point performance which is bulldozers weak point as it only has one FP unit per module. Integer performance then should be about double which would put it on par with sandy bridge.
For me personally, I am a big Folding@Home user. It can scale to 128 threads and only uses 64 bit floating point ops. Bulldozer will be amazing.
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new cpu needed for Aikoscence
this results are awsome (sorry for speaking like a kid), they really are ! sure!
actually i own a core i-975 (4-core 8-thread @3.33Ghz) for my 3d render (see www.aikoscence.com) are beginning boring (very long) and i need more power (time saving) to render in 480p (only 854x480).
so, if the simple SB core i5 can stand with a amd bulldozer, i'd rather to wait for the next extreme edition (6-core and 8-core) of the sandy bridge cpu (end of this year ??)
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Originally posted by indus View Post"since the CPUs are compatible with existing motherboards of the same socket types and there is no graphics support to worry about like there is with Fusion or Sandy Bridge".
This is incorrect.The bulldozer chips need an AM3+ socket and that is not equal to an 'existing' motherboard.
Enjoy.
It has already been reported that AMD's Bulldozer CPUs should be Socket G34 compatible with existing AMD Opteron 6000-series CPUs.
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"since the CPUs are compatible with existing motherboards of the same socket types and there is no graphics support to worry about like there is with Fusion or Sandy Bridge".
This is incorrect.The bulldozer chips need an AM3+ socket and that is not equal to an 'existing' motherboard.
Enjoy.
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Originally posted by smitty3268 View PostSource?
I think you're thinking of Bobcat, which they claimed would provide
For Bulldozer, the claims I've seen are 12% die space, and virtually double performance on the right kind of code. On the other hand, the wrong kind of code probably gives no speed up at all.
This source is pretty good at explaining how it works, as well as passing on AMD's 12% die space claim: http://www.anandtech.com/show/3863/a...t-chips-2010/4
But it's about a year older than your source so probably incorrect.
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