x86-64-v5? Questions Arise Over The Future Of x86-64 Micro-Architecture Feature Levels

[rmoog]

GCC now has the ability to pick the best library version for the arch anyway, right? Is anybody using that?

That's a glibc feature and it's called IFUNC.

[skeevy420]

Well, I would generally welcome that, since the x86-64-v4 (zen4/icelake) target could see a lot of improvements.
Doing this before Intel will ship AVX10 sounds also good as well as (maybe) introducing an own target for avx10, if required.

In CachyOS we thought also about this for long time, since the x86-64-v4 instructionset compared to the Zen4 is pretty different, but we didnt wanted to exclude some users from a generic march.
Maybe a dedicated repository would make sense, we have some computing power left which could do that.

Is there a project like GIMPS, a volunteered computing project, y'all could use so we could volunteer our systems towards building packages? Perhaps with a systemd timer to put the PC into volunteer mode?

My inspiration for that is my 7800X3D with 64GB of ram and an overkill Noctua cooler sits there doing nothing a lot of the time (especially overnight when I sleep), I don't have bandwidth restrictions anymore (AT&T moved into the area and suddenly the local cable telco had much better plans ), and I can guarantee 500GB of local storage space on my raidz in regards to building packages, source storage, and being able to stop/resume operations. I don't have a whole lot of money to give, but I do have a good PC that could help out.

[skeevy420]

That's a glibc feature and it's called IFUNC.

That sounds like a Parliament or Bootsy Collins song.

[CommunityMember]

That's a glibc feature and it's called IFUNC.

And one can always explicitly write code for testing for a feature and then using it (that was always the classic way of doing it, but with typically more developer overhead).

[geerge]

I believe instead of "mute point" you meant to write "moo point", as in a cow's opinion.

[ehansin]

I am a bit of a novice when it comes to CPU instruction set extensions. I am not clueless, but not exactly super knowledgeable. If anyone can clue me in on these parts, did some brief Wikipedia reading on AVX-512 and AVX10:

Sounds like AVX-512 requires 512 bit wide vector registers (if that is the correct term) and AVX10 can use 256 or 512 bit wide registers. Given, at least as I am understanding it, that AVX10 encompasses/supports (all?) AVX-512 instructions, does that mean a 256 bit wide AVX10 implementation supports some AVX-512 instructions by just using two registers? Just don't know enough here.

And if that is the case, curious where the main problems lies with compilers? I'm not arguing there are no problems, just don't know where the technical block is and am curious. Thanks as always.

[geerge]

I am a bit of a novice when it comes to CPU instruction set extensions. I am not clueless, but not exactly super knowledgeable. If anyone can clue me in on these parts, did some brief Wikipedia reading on AVX-512 and AVX10:

Sounds like AVX-512 requires 512 bit wide vector registers (if that is the correct term) and AVX10 can use 256 or 512 bit wide registers. Given, at least as I am understanding it, that AVX10 encompasses/supports (all?) AVX-512 instructions, does that mean a 256 bit wide AVX10 implementation supports some AVX-512 instructions by just using two registers? Just don't know enough here.

And if that is the case, curious where the main problems lies with compilers? I'm not arguing there are no problems, just don't know where the technical block is and am curious. Thanks as always.

tl;dr AVX512 introduces more than just an extension to 512 bits, there's actually a whole host of other crap some of which are nice 128/256 bit instructions that allow some things to be done cleaner than avx2 provides, avx2 does the job but it can be pretty clunky. AVX10 is intel retconning AVX512 because they realised they sucked at it as soon as AMD had something competitive, and intel need the die space to compete elsewhere. AVX10 256 bit is technically an upgrade over AVX2, it's basically all of the non-512 stuff in avx512, however everything is already written in AVX2 so the code that is ported to AVX10 256 will in most cases be a minor upgrade at best.

There's no technical block. Compilers just want to define a feature level, and future processors retconning the 512 bitness of v4 while being superior in some ways is an issue. On the face of it a v3.5 (avx10 256) and v5 (avx512 + avx10 512) might work, but there's been other instruction sets added in the meantime and intel has really just shat in a lot of devs cereal by trying to take their ball and go home.

[ehansin]

geerge Okay, thanks for the synopsis! I do get that creating different targets creates a mess. I'll be watching this some, know there will be more to come

[skeevy420]

Or it could end up being a mute point if the future Intel/AMD CPUs tend to go the 512-bit route in practice.

Michael
It's moot point.

[rmoog]

Michael
It's moot point.

Yep, it's moot point. It was called after the owner of 4chan (moot) trying to earn from advertising on the platform.