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Intel Details APX - Advanced Performance Extensions

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  • Intel Details APX - Advanced Performance Extensions

    Phoronix: Intel Details APX - Advanced Performance Extensions

    Following Advanced Vector Extensions (AVX) and more recently Advanced Matrix Extensions (AMX) for furthering the x86_64 CPU compute potential, Intel has now published initial details on APX: Advanced Performance Extensions...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    Why not introduce a new Microcode Architecture? That would allow full access to the microcode processor and therefore maximum performance...

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    • #3
      The amount of TLAs and ETLAs is too damn high...

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      • #4
        Originally posted by tildearrow View Post
        Why not introduce a new Microcode Architecture? That would allow full access to the microcode processor and therefore maximum performance...
        Elaborate please - how would changing the microcode architecture give fuller acccess to a (microcode processor?) and maximize performance in a way Intel has not been able to achieve currently? I'm seriously curious since I've never heard anyone complain about the microcode architecture before or have any proof it would give more performance since that sort of proof is not possible without literally building one or emulating at levels we can't do without proprietary intel beyond-red-book knowledge.

        If that prototype was faster, Intel would use it. They aren't smart enough or diabolical enough to think "I'll keep this in my pocket for 3 years and hope AMD doesn't figure it out, and use it before stock payout day after a few more years of low cost options lol".

        I wonder, if they start putting advanced uber specific cpu instructions behind a paywall, and some of those instructions would benefit kernel operations, how much yelling will happen when they go to upstream usage of said pay-only-optimizations into the kernel/gcc/etc. New faster instructions and more registers is always good if its not a subscription.

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        • #5
          X86 is becoming a larger mess than ever before. Wouldn't it be time to switch to a clean new design that was built from scratch? Those prefixes will hurt the performance and decrease instruction density.

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          • #6
            "APX Advanced Performance Extensions"? Interesting choice of naming. Hopefully more a success than Intel iAPX (Advanced Performance Architecture).

            I guess it would be nice to see the general purpose register set of x86 entering the ~~21st century~~ mid 1980s. Though it would be nice if we could just use a cleaner more modern ISA (RISC-V?) instead of tacking things on to x86. Either works, I guess.

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            • #7
              Originally posted by caligula View Post
              X86 is becoming a larger mess than ever before. Wouldn't it be time to switch to a clean new design that was built from scratch? Those prefixes will hurt the performance and decrease instruction density.
              Ok, but why? The entire selling point of Intel Architecture in the server/enterprise world is consistency - look how long its taken for epyc to get any sort of market share and thats the same instruction set... So what if I can recompile everything to target it? Will need years of tuning to get the compiler right and all the packages tuned. AVX512 is good example - its taken years for enough packages to support it for people to care and thats a bolt-on.

              Remember, Itanium was clean and built from scratch too. Intel has tried 'clean' and 'different' architecture before and failed, not because the tech was bad, Itanium was quite ahead of the game, but because the industry does not want to support multiple architectures in the DC. (ARM is trying but thats pretty specific cases where that arch is better than x86 in general.)

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              • #8
                Originally posted by ids1024 View Post
                Though it would be nice if we could just use a cleaner more modern ISA (RISC-V?) instead of tacking things on to x86.
                No thanks. If I wanted to be running RISC-V on my desktop machine, I would. I use x86 for the backwards compatibility and (currently) ARM for the tiny, low-power, fanless server that offers up stuff like NTP, Samba, and Netatalk to my DOS/Win98SE/WinXP/MacOS9 retro-hobby LAN.

                (It's a Cubox-i that I bought before RISC-V even existed as a Kodi box and repurposed as a server.)

                Maybe once we actually have a comparably performant open-source equivalent to Rosetta 2 in hand to run on existing non-x86 platforms and it's been proven to not be another case of "If you want to play early DirectX games, you need something which can run actual Windows 9x, because neither NT-based Windows nor Wine replicate certain niche DirectX features which were dropped later, and there are no accelerated VirtualBox/etc. guest video drivers for Win9x".

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                • #9
                  I'm curious how much coordination Intel does with AMD when they make these type of changes.

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                  • #10
                    Originally posted by jayN View Post
                    I'm curious how much coordination Intel does with AMD when they make these type of changes.
                    Dunno, but it's funny that every time AMD provide strong competition, Intel either a) play dirty, b) move the goalposts or occasionally, c) panic, borrow the idea and make out as if they did it first.

                    Subtext: competition good.

                    ...

                    Oh, goody, more ultra-specific extensions which allow Intel to win some benchmarks in [very specifically optimised software].

                    AVX-512 is a poor example to use for uptake of a particular set of extensions, as it has so many different things which all fit under the "AVX-512" umbrella but may or may not be present on the different hardware. I presume that this is an artefact of the Xeon Phi. I hope Intel won't repeat the same thing with AMX or this new proposed set of extensions.

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