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MIPS Claims "Best-In-Class Performance" With New RISC-V eVocore CPUs

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  • #1

    MIPS Claims "Best-In-Class Performance" With New RISC-V eVocore CPUs

    Phoronix: MIPS Claims "Best-In-Class Performance" With New RISC-V eVocore CPUs

    MIPS Tech is no longer working on their MIPS CPU instruction set architecture but has been taking on RISC-V based designs. Today the company made the bold announcement for their new eVocore P8700 and I8500 multiprocessor IP cores that they offer "Best-In-Class Performance and Scalability."..

    MIPS Claims "Best-In-Class Performance" With New RISC-V eVocore CPUs - Phoronix
    https://www.phoronix.com/scan.php?page=news_item&px=MIPS-New-RISC-V-May-2022
    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite
    Tags: None
  • #2
    This looks to be a big game changer for the Risc-V adoption, nice!
    • Likes 3

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    • #3
      Who owns MIPS these days? Does anyone trust them enough to do business with them?

      Comment

      • #4
        RISC-V desperately needs a sub-$100 SBC that can capture some mind-share. It needn't be fast, but it needs to run Linux. The hobbyist market right now is completely ceded to the Raspberry Pi.
        • Likes 10

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        • #5
          Originally posted by igxqrrl View Post
          RISC-V desperately needs a sub-$100 SBC that can capture some mind-share. It needn't be fast, but it needs to run Linux. The hobbyist market right now is completely ceded to the Raspberry Pi.
          At this point, I'd settle for *any* sub $100 SBC.
          • Likes 6

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          • #6
            Originally posted by willmore View Post
            Who owns MIPS these days? Does anyone trust them enough to do business with them?
            People do business with Oracle, Apple and Nvidia and they're the worst, so...
            • Likes 8

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            • #7
              It occurs to me that it should be easy to have "Best-In-Class Performance" when they are the only one in that class.
              • Likes 6

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              • #8
                Originally posted by ryao View Post
                It occurs to me that it should be easy to have "Best-In-Class Performance" when they are the only one in that class.
                It refers to Risk-V processors with 8 out of order execution ports. Plenty of x86 cores are at that level, the latest Intel core have 12 e-ports.

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                • #9
                  Originally posted by igxqrrl View Post
                  RISC-V desperately needs a sub-$100 SBC that can capture some mind-share. It needn't be fast, but it needs to run Linux. The hobbyist market right now is completely ceded to the Raspberry Pi.
                  Is $16.90 good enough for you for a "compute module" kind of board (different connector than Pi)?

                  https://www.aliexpress.com/item/1005003594875290.html


                  Or $20.90 bundled with a $5 expansion board, $23.90 with WIFI:

                  https://www.aliexpress.com/item/1005003741287162.html


                  Or $29 for one with the same SoC but on a Pi CM3 compatible board:

                  ClockworkPi Core R-01 | ClockworkPi
                  https://www.clockworkpi.com/product-page/copy-of-clockworkpi-core-r-01
                  The ClockworkPi Core R-01 is a single-core 64-bit RISC-V module with limited performance, it does not include GPU acceleration.However, the RISC-V ecosystem is growing fast. We are pleased to be able to provide you with the latest, usable, low-cost RISC-V compute module, build the most direct connection to the RISC-V community for you. Please note: ClockworkPi Core R-01 is a highly experimental model and requires some experience with Linux system & FOSS. We strongly recommend all beginners to choose other models. What is RISC-VRISC-V is an open standard instruction set architecture (ISA) that began in 2010 and is based on established reduced instruction set computer (RISC) principles. RISC-V is provided under open source licenses. Learn more at RISCV.org Tech Specs RISC-V Single-core RV64IMAFDCVU @ 1.0GHz (maximum frequency) No GPU (software rendering only) 1GB DDR3 memory The 200pin SODIMM interface is compatible with CPI v3.14 mainboard Size: 67x30mm DocumentationD1 Datasheet: https://github.com/clockworkpi/DevTerm/blob/main/D1_Datasheet_V0.1_Draft_Version.pdfD1 User Manual: https://github.com/clockworkpi/DevTerm/blob/main/D1_User_Manual_V0.1_Draft_Version.zipD1 wiki: https://linux-sunxi.org/D1 Shipping information Express service Based on the current supply chain and logistics situation, the estimated delivery time is approximately 60 business days.


                  This SoC is roughly Pi Zero class. Runs Linux, with 512 MB or 1 GB RAM depending on exactly which of the above boards you get. Not fast but you said that's OK.
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                  • #10
                    Originally posted by artivision View Post

                    It refers to Risk-V processors with 8 out of order execution ports. Plenty of x86 cores are at that level, the latest Intel core have 12 e-ports.
                    It says 8 fetch, so possibly 8 decode too. Generally you have 1.5-2x as many execution ports than decoders. But width doesn't say much about performance.

                    There are some very odd design choices here: there is a shared L2 cache and SMT, but no mention of L3 or SIMD extension. A cluster only has about 64 GB/s bandwidth shared between 8 cores. All this tells me this won't be a high performance design, certainly not something suitable for a many-core server. It may well beat current RISC-V cores, but that's a pretty low bar.
                    • Likes 1

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