AMD SMM Callout Privilege Escalation Bug Disclosed For APUs

[hotaru]

It's obviously not that fast, but being dead simple means it's very energy efficient and small so it gets used a lot in big.Little-setups as the "Little" part.

turns out it's actually not all that energy efficient. comparing the ODROID-N2 and ODROID-C4 shows that a combination of A73 and A53 is more energy efficient than A55, and ARM claims that A55 is 15% more energy efficient than A53.

[L_A_G]

turns out it's actually not all that energy efficient. comparing the ODROID-N2 and ODROID-C4 shows that a combination of A73 and A53 is more energy efficient than A55, and ARM claims that A55 is 15% more energy efficient than A53.

Did you get the A53 and 55 mixed up there because I was talking about the A53. As for the comparison, you do realize that the A53-based "Little" part of the big.Little setup in the N2 is dual core and the non-big.Little setup in the C4 is quad core? It's pretty apples-to-oranges kind of comparison you're making there.

[hotaru]

Did you get the A53 and 55 mixed up there because I was talking about the A53. As for the comparison, you do realize that the A53-based "Little" part of the big.Little setup in the N2 is dual core and the non-big.Little setup in the C4 is quad core? It's pretty apples-to-oranges kind of comparison you're making there.

the point is that the A73 is more efficient than the A55, which is in turn more efficient than the A53, so the A73 is definitely more efficient than the A53.

[L_A_G]

the point is that the A73 is more efficient than the A55, which is in turn more efficient than the A53, so the A73 is definitely more efficient than the A53.

You do know that the A73 is one ARM's "big" cores and most definitely not on the same efficiency level as their "small" cores like the A53 and A55? It's often paired up with A53s precisely for reasons of efficiency.

Comparing a big.Little setup to a "One core type to rule them all"-type solution is obviously going to yield a result in favor of the big.Little setup as those are specifically designed to be efficient regardless of the workload. In the ODroid example you're using the AMLOGIC solution with 4 efficiency cores obviously won't be more efficient than another AMLOGIC solution with 2 performance cores in high load scenarios nor is it going to be as efficient as half as many efficiency cores in low-load scenarios.

However where it does win majorly is in cost as that fixed 4 efficiency core setup without the bulk of the "big" cores and additional big.Little logic is going to fit on a much smaller die, which means you get more dies per wafer and with more dies per wafer you also get better yields. Hence it's very obviously an apples-to-oranges kind of comparison you're trying to make here.