Intel Details New Data Streaming Accelerator For Future CPUs - Linux Support Started

[coder]

Separate or integrated into the CPU die?

It should be on-die.

If it were larger, I'd just say "in-package". However, something like this is probably much too small to put on its own die. Maybe as part of an "I/O die", if Intel follows AMD's Zen2 approach...

[timofonic]

I’m not so sure, it sounds more like an intelligent I/O processor than any thing else. Hopefully more info will come soon.

Separate or integrated into the CPU die?

[wizard69]

Still sounds like every chain-able DMA Hardware I ever worked with? Every SOC nowadays has these without Phoronix going bonkers about it.

I’m not so sure, it sounds more like an intelligent I/O processor than any thing else. Hopefully more info will come soon.

[discordian]

It's actually not a bad idea, if done right. Sounds a bit like mainframe-style channel I/O, which would be really amazing.

Still sounds like every chain-able DMA Hardware I ever worked with? Every SOC nowadays has these without Phoronix going bonkers about it.

[HyperDrive]

Back to the past. Old DMA resurrected again.

Do we live in circles?

Will we see the resurrection of Amiga architecture too? Copper?

It's actually not a bad idea, if done right. Sounds a bit like mainframe-style channel I/O, which would be really amazing.

[timofonic]

Back to the past. Old DMA resurrected again.

Do we live in circles?

Will we see the resurrection of Amiga architecture too? Copper?

[cynical]

Considering that Intel messed up memory security, and switching between user and kernel space got more expensive due to that, this seems like a bad attempt to mitigate the performance loss. I'm worried that the complexity of this feature will cause just more security nightmares.

Aren't they pushing some new special memory for the same reasons? I recall reading about that somewhere...

[coder]

Wow, I figured Hyper Threading killed DMA, but this sounds like DMA on steroids. One benefit might be lower-overhead/lower-latency context switching between data streams, in addition to simply being able to handle more data streams than you'd care to burn hyperthreads on.

a Non-Transparent Bridge (NTB) device to/from remote volatile and persistent memory on another node in a cluster.

That even sounds a bit like taking on the NVLink use case, or at least a piece of it. Of course, there still needs to be a capable PHY, but at least this might be able to handle the routing.

[mrugiero]

Considering that Intel messed up memory security, and switching between user and kernel space got more expensive due to that, this seems like a bad attempt to mitigate the performance loss. I'm worried that the complexity of this feature will cause just more security nightmares.

Maybe they hurried it up because of those reasons, but this seems valuable by itself, so it was probably in store even before these issues came to light.
I may be naive.

Considering that Intel messed up memory security, and switching between user and kernel space got more expensive due to that, this seems like a bad attempt to mitigate the performance loss. I'm worried that the complexity of this feature will cause just more security nightmares.