Mainline Linux Support Getting Squared Away For $129 Intel SoC FPGA Board

[phoronix]

Phoronix: Mainline Linux Support Getting Squared Away For $129 Intel SoC FPGA Board

Patches for the board support for the Chameleon96 Intel FPGA board have been published and could soon be found in the mainline Linux kernel...

http://www.phoronix.com/scan.php?page=news_item&px=Intel-FPGA-Chameleon96-DTS

[marty1885]

Cortex A9... Serious?
I have worked with the exact same SoC. And it has been the worst experience I have ever.

[starshipeleven]

Cortex A9... Serious?
I have worked with the exact same SoC. And it has been the worst experience I have ever.

Story time?

[marty1885]

Story time?

First of all. Coretx A9 on the SoC is simply hot as hell. My evaluation bored fried serval times without a fan. (Fortunately Terasic is kind enough to fix that for free as they find out the problem). And the A9 core are so slow that they can't decode a 480p H264 video. Making video related projects nearly impossible. Adding salt to injury, the Cyclone V SoC don't have an on chip GPU. It has to drive HDMI through FPGA while relying on the two weak CPUs to draw everything; making the entire situation worse.

While one of the selling point of Cyclone V is it supports OpenCL using the included FPGA. Yet the toolchain is horrible. The OpenCL compiler crashes realiably when a program includes a 3 layer nested loop. And it takes at least 1hr to generate the FPGA bitstream for any OpenCL kernel.

Well although the tools are horrible. the FPGA OpenCL stuff is really Amazing. For a CS and research perspective. I don't think it's worth the hussle for makers and the daily devs. The compile time is simply not acceptable.

[discordian]

First of all. Coretx A9 on the SoC is simply hot as hell. My evaluation bored fried serval times without a fan. (Fortunately Terasic is kind enough to fix that for free as they find out the problem). And the A9 core are so slow that they can't decode a 480p H264 video. Making video related projects nearly impossible. Adding salt to injury, the Cyclone V SoC don't have an on chip GPU. It has to drive HDMI through FPGA while relying on the two weak CPUs to draw everything; making the entire situation worse.

While one of the selling point of Cyclone V is it supports OpenCL using the included FPGA. Yet the toolchain is horrible. The OpenCL compiler crashes realiably when a program includes a 3 layer nested loop. And it takes at least 1hr to generate the FPGA bitstream for any OpenCL kernel.

Well although the tools are horrible. the FPGA OpenCL stuff is really Amazing. For a CS and research perspective. I don't think it's worth the hussle for makers and the daily devs. The compile time is simply not acceptable.

Summary: If you don't plan to develop on the FPGA, dont use a board that centered around developing on a FPGA.

[starshipeleven]

Summary: If you don't plan to develop on the FPGA, dont use a board that centered around developing on a FPGA.

summary: if you can't read on your own please ask an adult to do it for you.

He made pretty clear that he actually was developing OpenCL stuff on the FPGA. He said that "the FPGA OpenCL stuff is really Amazing" and talked about OpenCL compiler.

His point here is that while the FPGA is great, the rest of the SoC is garbage and hampers the FPGA's job, and also that the OpenCL toolchain to run stuff on the FPGA is garbage, so the OVERALL experience is very bad.

[marty1885]

Summary: If you don't plan to develop on the FPGA, dont use a board that centered around developing on a FPGA.

Sorry for my words not being clear enough. starshipeleven has explained pretty clear. Thanks!


I once developed an OpenCL neural network accelerator on the FPGA for pedestrian detection. The NN accelerator endded up being able to process 480p images @ 120FPS with very low latency (1 image per batch, no pipelining, only getting 3FPS out of the CPUs). BUT due to decoding video stream being the bottleneck (handled by the both the A9 cores. To be clear). I can only run the detection at 12 FPS.

--Edit--
In my opinion. The SoC should have at least 4 A53 cores and a basic GPU (hopefully also with OpenCL support). That shoukd make the SoC a lot cooler and gives it extra computing power to handle real world work loads.

[StefanBruens]

In my opinion. The SoC should have at least 4 A53 cores and a basic GPU (hopefully also with OpenCL support). That shoukd make the SoC a lot cooler and gives it extra computing power to handle real world work loads.

Have a look at the Ultra96 - Xilinx Zynq® UltraScale+ MPSoCs
Costs two times as much (249 $US), but has 4x A53, Mali400-MP2, USB 3.0 in/out (instead of 2.0), 2GByte RAM (instead of 0.5), ...
No first hand experience, though.

[discordian]

Sorry for my words not being clear enough. starshipeleven has explained pretty clear. Thanks!


I once developed an OpenCL neural network accelerator on the FPGA for pedestrian detection. The NN accelerator endded up being able to process 480p images @ 120FPS with very low latency (1 image per batch, no pipelining, only getting 3FPS out of the CPUs). BUT due to decoding video stream being the bottleneck (handled by the both the A9 cores. To be clear). I can only run the detection at 12 FPS..

Your application is a very specific one then and would require a GPU. There are alot reasons to use a FPGA without any video decoding involved (logic analyzers, high precision control, precise emulation of old hardware) - which this board is a nice entry-level for.

OpenCL is more of a high-end application for FPGA, and has several overlaps with GPUs anyway.

[Zyklon]

Have a look at the Ultra96 - Xilinx Zynq® UltraScale+ MPSoCs
Costs two times as much (249 $US), but has 4x A53, Mali400-MP2, USB 3.0 in/out (instead of 2.0), 2GByte RAM (instead of 0.5), ...
No first hand experience, though.

Does the Ultra96 have mainline support?