AMD Next Horizon: Zen 2, 7nm Vega, AMD On Amazon EC2

[mercurio]

Wish for Oracle Solaris to run on AMD Epyc, so far Oracle announced X7 series aimed for Cloud.

[xxmitsu]

I would have expected AMD to double the number of CU, as the die size has shrunk significantly.

I expect the new process node is very expensive with the raise of the silicon area. Or might even not be mature enough so that it would have good yields with a larger die.
So I suppose that increasing the number of CUs would lead to a larger die .. more expensive silicon and fewer cards made in time unit. Not no mention probably also a bit of re-architecture here and there.

[cb88]

The Vega 7nm announcement seems to have been more 'lower power, better fp64, int4 and bandwith', but apparently same fp32.
That's surprising they predict 1.25x performance for same power, but 50% power use for same performance. Shouldn't it be a bit more ?
I would have expected AMD to double the number of CU, as the die size has shrunk significantly.

Zen 2 seems quite exiting on the other hand.

It's an Pro/AI compute card and those tend to have lower clocks than Gaming cards. A 7nm gaming GPU on this process in it's current state would probably hit 2Ghz easily in a liquid cooled version. And again consider that the gaming version would have smaller CU probably a little faster than this there too since they wouldn't have to support DPFP.

[anth]

Chiplet? Isn't it "chipset"?

Chiplet was correct. Future Epyc processors will combine Zen 2 CPU chiplets fabbed at 7nm with an I/O and memory access chiplet fabbed at 14nm. Current Epyc (and Threadripper) already use multi-chip modules, this adds some specialisation to the dies including in those.

[mzs.112000]

I wish AMD would put out a laptop chip, that could have 8 cores/16 threads, run at 4.5GHz, and have 45W TDP....
Then, do a Vega 32 or the like for graphics. That would be nice...

[cb88]

Chiplet was correct. Future Epyc processors will combine Zen 2 CPU chiplets fabbed at 7nm with an I/O and memory access chiplet fabbed at 14nm. Current Epyc (and Threadripper) already use multi-chip modules, this adds some specialisation to the dies including in those.

Chiplets are the smaller dies the 7nm ones, the 14nm die isn't a chiplet its the IO hub die.

[Jabberwocky]

Michael Chiplet? Isn't it "chipset"?

Also, is Zen 4 in design stages or did you mean Zen 3?

Zen 4 is correct, these designs take many years to complete. Zen 3's target is 2020 and they need to plan for 2021 in (or before) 2018.

Edit: I am not sure about the definition of chiplet, but in this case it's piece of logic within the CPU p̵e̵r̵h̵a̵p̵s̵ ̵a̵ ̵C̵C̵X̵ which bundles the CCX(s) memory controller and various other logic. The chiplets are routed together via interposers which forms the CPU as a whole. Either way it's not the CPU and it's not a single core. Not sure if you can technically call it a chipset, but chiplet is definitely a better description.

Better explanation here: https://youtu.be/G3kGSbWFig4?t=43

[M@yeulC]

The Vega 7nm announcement seems to have been more 'lower power, better fp64, int4 and bandwith', but apparently same fp32.
That's surprising they predict 1.25x performance for same power, but 50% power use for same performance. Shouldn't it be a bit more ?
I would have expected AMD to double the number of CU, as the die size has shrunk significantly.

Zen 2 seems quite exiting on the other hand.

Nah, you start to lose on power efficiency at the transistor level under 22nm, due to tunnelling currents among others (AFAIK, that is, I am not really familiar with TSMC 7nm).

What continues to improve as usual is the integration density; AKA the number of transistors. You can use it to design smarter chips, but nowadays performance really hits a thermal ceiling, and 7nm doesn't help with this, almost the contrary. So it's still quite impressive that they can squeeze as much power as this in the first place

I guess you could separate the dies and put bigger cooling systems, but my Fury already has 300W of TDP, and my PC case reaches 80°C. Long-term, the battle is in alternative architectures, and improving power efficiency for on-chip interconnect. I have no idea how HBM fares, it might help a bit, but AMD has some nice IP with their infinity fabric. Next up might be some photonic on-chip interconnect

[Adarion]

AMD supported coreboot for years in the past. It was a huge amount of work. Unfortunately, no one did much with it. I don't know if there are plans to restart it. I'm not sure what sort of demand there is for it in general.

Come on, you can hear "Coreboot" "Librecore" "Libreboot" near daily here, it was (among?) the most upvoted question at the Reddit AMA with Lisa, so there surely is demand.
This is maybe more a chicken / egg problem. In the past lots of vendors, esp. normal consumer mainboard vendors went with the UEFI crap, partially because it was forced down their throat, partially because they fear W32 incompatibilities and partially because they could place terminally stupid animations of spinning fans in the "BIOS"/firmware setup menu. And even more silly things. (e.g. probably unintentional, but white text on white BG due to a light reflection on a modified photo, ended up not being able to read iirc. memory timings in a Biostar mainboard setup, really awesome...)

Moreover we all know UEFI is a sheer pest. Do I really have to quote the countless sources? There hardly is a week without some new horror issue, bricked boxes, security issues, backdoors etc. to read on the newslines. It's broken by design.

Futhermore - "no one did much with it". We would have loved, but there were still those mainboard vendors (let aside smaller runs like PC Engines and the likes). And you probably have to adjust at least parts to each mainboard series of a vendor. It's nothing end users easily do on an afternoon. And without some support from mainboard vendors / manuf. or SIO/EC makers, things are harder to achieve.

And, seriously, please shed some light upon the "huge amount of work". Was is legal issues, lots of questions from the external devs regarding memory initialisation,...? Maybe there are points of friction that could be reduced, or that are no longer valid.

[ms178]

Right now all the reports say it will be AVX2 only. With more support for AVX-512 in the application field, this could change. If they did, I would guess only AVX-512F would be the subset.

FMA4 support was announced by AMD for all Zen iterations awhile back.

My point with the FMA4 analogy was that I hope their implementation won't be ISA incompatible with the AVX512 instruction set, The reports were a bit light on this important detail. The performance claims indicate AVX512 support as they are doubling the vector widths. It seems plausible that they continue to use their double-fuse technique which they used with Zen 1 to get AVX2 compliant. Intel's implementation took less clock cycles but AMD's implementation would suit them better if only 128 bit vectors were required. If they were targeting Icelake with Rome they'd better be AVX512 compliant by now in my opinion as it is already long in the works and should have been made available in 2016 originally with Cannonlake to the masses. In the HPC world there are already workloads which can take advantage of this, especially in numerical computation heavy workloads where Naples was not that competitive. Using the same code path would bring the benefit of leveraging Intel's own investments into the software ecosystem to their advantage.