Originally posted by jacob
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There is a reason why you want a hyper-visor without over-commit.
Its in the risc-v prototypes. Labeled Risc-V.
The reality is if you want to user a hypervisor and have real-time performance in one of the VM on a multi core chip you will be doing it different to the way Xen and KVM have been done.
Siemens does a lot of medical items. Now getting a in kernel hyper-visor design to support the likes of Labeled Risc-v means they would be able to use a multi core chip and safely delicate sections of it to performing real-time tasks like like controlling a MRI scanner of course once the scan is complete be able to shut the real-time process down and use that core/cores for general processing.
Remember with aviation and medical certification design can take 4 to 5 years. So starting the jailhouse hypervisor now could be for what silicon will look like 4-10 years into the future. With risc-v particularly when can see the stuff being worked for 4-10 years into the future.
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