L2 CDP Added To Linux 4.16 For L2 Cache Partitioning On Intel CPUs

[phoronix]

Phoronix: L2 CDP Added To Linux 4.16 For L2 Cache Partitioning On Intel CPUs

L2 Code and Data Prioritization (L2 CDP) is a feature of Intel's Resource Director Technology (RDT) that will now be supported with the Linux 4.16 kernel...

http://www.phoronix.com/scan.php?page=news_item&px=Linux-4.16-L2-CDP-RDT

[schmidtbag]

This seems to be something Ryzen would heavily depend on. From what I noticed, the most significant performance losses in Ryzen have to do with exchanging data between caches. If you could partition the cache for a specific application, that could dramatically improve performance.

[duby229]

This seems to be something Ryzen would heavily depend on. From what I noticed, the most significant performance losses in Ryzen have to do with exchanging data between caches. If you could partition the cache for a specific application, that could dramatically improve performance.

Actually I'm pretty certain that's the L3 cache adding latency. It's not an inclusive cache, it doesn't keep the entire contents of every L2 below it, it only collects what was evicted from the L2 caches below it. And then the whole problem gets even more exacerbated by the way inter-CCX latency works. If it was inclusive then I think latency from the cache hierarchy would be a lot better.


https://www.techpowerup.com/231268/a...cx-compromises

[schmidtbag]

Actually I'm pretty certain that's the L3 cache adding latency. It's not an inclusive cache, it doesn't keep the entire contents of every L2 below it, it only collects what was evicted from the L2 caches below it. And then the whole problem gets even more exacerbated by the way inter-CCX latency works. If it was inclusive then I think latency from the cache hierarchy would be a lot better.

Yes, I was pretty sure it was the L3 specifically, but I wasn't entirely sure so I was intentionally ambiguous about the way I phrased my post. I think partitioning the L3 would still offer a hefty performance improvement, by (in a way) addressing the problems you mentioned.

[duby229]

Yes, I was pretty sure it was the L3 specifically, but I wasn't entirely sure so I was intentionally ambiguous about the way I phrased my post. I think partitioning the L3 would still offer a hefty performance improvement, by (in a way) addressing the problems you mentioned.

Well the thing is that Intel CPUs only experience the latency of the l3 cache, but AMDs experience the latency of l2 + l3 + inter-CCX. A good prrogrammer could sort of keep inter-CCX latency to a minimum, but there is nothing he can do about l2 + l3 latency.