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Libre-SOC Still Persevering To Be A Hybrid CPU/GPU That's 100% Open-Source

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  • Libre-SOC Still Persevering To Be A Hybrid CPU/GPU That's 100% Open-Source

    Phoronix: Libre-SOC Still Persevering To Be A Hybrid CPU/GPU That's 100% Open-Source

    The project that started off as Libre-RISC-V with aims to be a Vulkan accelerator but then decided on the OpenPOWER ISA rather than RISC-V is still moving ahead under the "Libre-SOC" branding...

    http://www.phoronix.com/scan.php?pag...Libre-SOC-2020

  • #2
    Found a typo: ... SoC would haven o DRM ...

    Comment


    • #3
      As I understand it, they had no good reason to switch from RISC-V.

      It's just, the person running the project is incapable of working with others and did make no effort to understand/work within RISC-V processes.

      They got called out for it, and their response was to force a switch to openpower in retaliation.

      I honestly don't expect much from the project, when the leadership is like this.

      Comment


      • #4
        If you look through their website, you'll see that this is a laughable effort, run by people who have no understanding of how to actually build a modern SoC.
        The fact that this talk was accepted to any venue shows a lack of research on the organizer's parts.

        Several examples of this project's incompetence
        • Continually pushing for a magic "CPU/GPU/VPU" architecture without any hard evidence of the advantages of such a design
        • No clear micro-architecture, or even block diagram after years in development. The one in the slide deck is so simple as to be useless.
        • No quantitative analysis behind any of the numbers in their presentation. How are they generating these area/power numbers? They don't even have performance numbers for what they claimed to be a application-class SoC? The lack of a quantitative analysis on any of this project's "novel ideas" shows that they fundamentally misunderstand how SoC development is performed
        • They base the crux of their core's performance on a magical CDC6600-derived design, ignoring that the instruction scheduling is only one tiny part of overall core performance. What about the memory system? Branch prediction? Power management?
        • Basing their design on MicroWatt, a tiny soft core
        It's just, the person running the project is incapable of working with others and did make no effort to understand/work within RISC-V processes.
        Yep. The RISC-V "process" (which is really the process for any well-run community-driven project) is that proposals should have quantitative evidence of their usefulness towards the general community in order to be considered. Luke's regularly bullied anyone who asked for quantitative evidence behind his handwavy arguments and questionable anecdotes, and refused to acknowledge the RISC-V community's very reasonable requests.

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        • #5
          Sounds like a lot of work... Meanwhile, my Raspberry Pi 4 is doing the job pretty well. Maybe it's not open source hardware wise, but sheesh, it's so cheap and works so well, how can I pass it up?

          Even if these guys were successful at creating a performant 100% open source hardware design, they've still got to build the things. Like it or not, Broadcom and the Raspberry Pi Foundation have economies of scale that will be challenging to beat.

          I don't see how these guys will be successful, but good luck to them!

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          • #6
            Originally posted by ed31337 View Post
            Even if these guys were successful at creating a performant 100% open source hardware design, they've still got to build the things. Like it or not, Broadcom and the Raspberry Pi Foundation have economies of scale that will be challenging to beat.

            I don't see how these guys will be successful, but good luck to them!
            Actually the RPis aren't even the cheapest, nor best-valued devices out there. However, for anyone not familiar with ARM, I would recommend them since the RPi community is probably the most useful.

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            • #7
              Originally posted by ayumu View Post
              As I understand it, they had no good reason to switch from RISC-V.

              It's just, the person running the project is incapable of working with others and did make no effort to understand/work within RISC-V processes.
              I think that part of the problem is that Risc-V has NDAs. Doesn't that seem a little non-transparent to you?

              Comment


              • #8
                I hope this project is a success. I am not sure if it is fair to use the EOMA68 project as a predictor because factors could be different. Execution is difficult and hopefully there are lessons learned from EOMA68 that help this project.

                Comment


                • #9
                  Originally posted by TJSER View Post
                  If you look through their website, you'll see that this is a laughable effort, run by people who have no understanding of how to actually build a modern SoC.
                  The fact that this talk was accepted to any venue shows a lack of research on the organizer's parts.
                  Over the years good science have been rejected by conferences and publications for not meeting arbitrary standards. It is actual;y good that the outlier and even the flaks get a chance to put their ideas out there.

                  Several examples of this project's incompetence
                  • Continually pushing for a magic "CPU/GPU/VPU" architecture without any hard evidence of the advantages of such a design
                  • No clear micro-architecture, or even block diagram after years in development. The one in the slide deck is so simple as to be useless.
                  • No quantitative analysis behind any of the numbers in their presentation. How are they generating these area/power numbers? They don't even have performance numbers for what they claimed to be a application-class SoC? The lack of a quantitative analysis on any of this project's "novel ideas" shows that they fundamentally misunderstand how SoC development is performed
                  • They base the crux of their core's performance on a magical CDC6600-derived design, ignoring that the instruction scheduling is only one tiny part of overall core performance. What about the memory system? Branch prediction? Power management?
                  • Basing their design on MicroWatt, a tiny soft core
                  While I don't track what is going on with this project in detail, I did for awhile track the development of Parallax's Propeller processors. So consider this:
                  1. Sometimes even the developer doesn't understand all the advantages of his architecture. A surprising number of people have created a significant niche for Propeller. I'd really would hate to see a world where people are not permitted to explore these sorts of unusual designs.
                  2. Well that can be an issue, one thing that Parallax has done well is to communicate.
                  3. From what I've seen this is far from "applications class" based on what I expect out of a processor these days. In any event the point here is that they don't understand SoC development from your point of view. There is no reason to believe that SoC development has to follow any specific model of development.
                  4. So how long did they have to do this presentation? You can liken this to an Apple event, they only gloss over their processors but any rational evaluation of those A series processors is that they perform well.
                  5. Not up to speed on MicroWatt. However it really depends upon what your mean by "basing", are they borrowing low power design concepts. If so that may very well be a smart move.
                  By the way I'm not defending RISC-V nor this project as I consider both of them to be long shots for a sustainable future. All I know is that the history of Propeller indicates that a successful project can start from one mans effort, with really thin data and morph into a successful product. Will Libre-SOC go this route? I highly doubt it to be honest but that shouldn't stop anybody from pursuing their dream.

                  Yep. The RISC-V "process" (which is really the process for any well-run community-driven project) is that proposals should have quantitative evidence of their usefulness towards the general community in order to be considered. Luke's regularly bullied anyone who asked for quantitative evidence behind his handwavy arguments and questionable anecdotes, and refused to acknowledge the RISC-V community's very reasonable requests.
                  RISC-V is hardly useful to the "general community" so by that measure the complete project is a failure.

                  Comment


                  • #10
                    Originally posted by ayumu View Post
                    As I understand it, they had no good reason to switch from RISC-V.
                    the reason is simple: the RISC-V Foundation failed, in direct violation of Trademark Law and responsibilities, to respond to repeated in-good-faith requests that our unique combination of business requirements be taken into account, and that we be allowed to participate freely and fully transparently in the ongoing enhancement and development of the RISC-V ISA.

                    if we had signed the secret agreements demanded of us, and engaged in the (demanded) practice of discussing ISA developments secretly behind closed doors, then our business objectives would have been completely destroyed and undermined, on the basis that any business claiming to be fully transparent by offering their customers full access to an independently auditable development process, who then entered into *secret* closed-doors proprietary development could rightly be accused of total utter hypocrisy.

                    so there are in fact very good reasons indeed, ayumu, and thank you for bringing up the matter so that it can be clarified.

                    It's just, the person running the project is incapable of working with others and did make no effort to understand/work within RISC-V processes.
                    i took great care to understand RISC-V and its processes. i made every effort - for 18 months - to gain access to the RISC-V processes and procedures in ways that did not catastrophically compromise our business objectives to provide a fully-transparently developed SoC.

                    every single time i did not receive a response.

                    the RISC-V Foundation Board of Directors failed - repeatedly - in their responsibility and duties - to respond to those in-good-faith requests for our team's unique circumstances to be taken into account.

                    if we had even compromised *in the slightest* on the full transparency requirements, then not only would customers be fully justified in saying "these people are not in the slightest bit serious, they compromised their integrity right at the start", but NLnet - our funding body - could also claim that we had deceived them in our Grant Applications.

                    and that's *fraud*, ayumu!

                    does that help explain why i had to take this so seriously?

                    and the reason why we switched to OpenPOWER is because after 18 months i simply got sick and tired of the systematic failure of the RISC-V Foundation to honour its legal obligations under Trademark Law.

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