Following Linux's UEFI code getting cleaned up earlier this year in preparation for RISC-V support being added and then some early RISC-V UEFI patches, a more comprehensive set of patches for enabling UEFI support on RISC-V under Linux have been sent out.

The RISC-V architecture code in the Linux kernel continues seeing more improvements for running on real hardware and seeing other capabilities introduced.

The RISC-V architecture changes have been submitted for the Linux 5.7 kernel and includes early work on bringing up a new RISC-V dual-core SoC.

As we've been expecting to happen with the Linux EFI code being cleaned up before the introduction of a new architecture, the RISC-V patches have been posted for bringing up UEFI boot support.

RISC-V's Supervisor Binary Interface "SBI" is the interface between the platform-specific firmware and the running operating system or hypervisor for interacting with the supervisor execution environment in the higher privileged mode. The Linux kernel has been working to support a newer version of the SBI that is more extensible moving forward.

While still a draft standard, support for the RISC-V "V" Vector Extension support for the Linux kernel is currently being prepared.

Libre RISC-V, the project aiming to create an open-source accelerator that would run a Vulkan software renderer in being an "open-source GPU" aiming for just 25 FPS @ 720p or 5~6 GFLOPS, has managed to secure 300k EUR in grants for their work.

While there has been the Libre RISC-V community-driven effort to create a RISC-V graphics processor that basically amounts to a RISC-V core with vector extensions/improvements and running a Vulkan software implementation (though they are now reportedly eyeing POWER instead of RISC-V), Think Silicon has announced the first actual RISC-V ISA based 3D graphics processor.

The RISC-V kernel code has some interesting changes ready for Linux 5.5.

There is much greater performance potential out of RISC-V now with SiFive having announced the U8-Series.

Well, here is a surprise... The Libre RISC-V project that is trying to build an "open-source GPU" more along the lines as a Vulkan accelerator is looking at other options besides RISC-V. While RISC-V is royalty-free and open-source in nature, Luke Kenneth Casson Leighton is not content with the RISC-V Foundation and is evaluating the likes of POWER and MIPS.

To date there haven't been any really compelling RISC-V processors from a performance perspective but it's looking like we could soon be crossing that threshold.

In-step with more RISC-V hardware becoming available over time, the Linux kernel architecture support for RISC-V has continued maturing and with Linux 5.3 is in better shape.

Keith Packard has joined RISC-V company SiFive. Yes, the same Keith Packard that is the longest still active (though somewhat more dormant these days) X Window System developer who for many years had led much of the X11/X.Org efforts and worked for nearly a decade at Intel on their open-source Linux graphics driver stack before working for HP Labs and also a side-gig for Valve improving the Linux stack for VR.

The very ambitious project working on an open-source RISC-V architecture to serve as a Vulkan accelerator for 3D graphics secured a minor victory last week with receiving $50k EUR from the European Commission's Next Generation Internet initiative. They will be using these funds to allow for full-time engineering work and bounty-style tasks to work on this "100% libre RISC-V + 3D GPU chip for mobile devices."

If you want a SiFive SoC for the royalty-free, open-source RISC-V architecture it's now possible to pair it with graphics. Unfortunately, the graphics option is about as far from open-source as possible.

SiFive has announced an upgraded Freedom Everywhere SoC as well as the HiFive1 Revision B developer board using this FE310-G002 SoC.

The Linux kernel's RISC-V processor support is getting into good shape now since the support for this open-source processor ISA was originally introduced back for Linux 4.15. Moving forward, it's now expected the support to be maintained and only improve for the HiFive Unleashed developer board.

Amazon AWS has added support for the RISC-V open-source processor architecture to their FreeRTOS kernel.

The mainline GNU GRUB boot-loader now supports the RISC-V architecture as another important step for better mainline support for this new, royalty-free processor ISA.

Besides having a dedicated Intel GPU to look forward to in 2020, the effort around creating an open-source RISC-V architecture based graphics processor continues being spearheaded by Luke Kenneth Casson Leighton and other libre hardware developers.

RISC-V remains of a lot of interest to open-source/Linux users for being a royalty-free and completely open CPU architecture. In part due to the lack of affordable RISC-V hardware limiting developers from working more on this architecture, the state of RISC-V support by Linux distributions varies but at least has improved a lot in recent years.

With the proposed Libre RISC-V Vulkan accelerator aiming to effectively be an open-source GPU built atop the open-source RISC-V ISA there were recently some new details published on how the design is expected to work out.

For those interested in the proposed quad-core RISC-V Libre SoC that is intended to go in-step with the Rust-written Kazan for offering Vulkan support, the initial performance target has now been shared.

More than a year ago Western Digital talked up how they would begin designing RISC-V cores and shipping them in devices and that is indeed panning out. The company has unveiled their new SweRV core and plans to open-source it in 2019.

Stemming from the recent proposal about a libre GPU using a RISC-V chip running a Rust-based software renderer like a software-based Vulkan implementation, the developer appears to be ready to take on designing a quad-core RISC-V libre SoC that he believes can be competitive for mobile devices.

The Linux Foundation and RISC-V Foundation are announcing a joint collaboration effort today to promote open-source development and adoption around this royalty-free CPU instruction set architecture.

SiFive this week announced their 7-Series RISC-V cores with the 32-bit E7, 64-bit S7, and 64-bit U7 series. These new RISC-V parts aren't yet capable of running up against the fastest ARM Cortex CPU cores available today, but they are much more powerful than the previous-gen SiFive cores.

With the increasingly popular RISC-V open-source processor instruction set architecture (ISA), there is the possibility for vendor-specific instruction set extensions. At this point the kernel has no infrastructure in place for its RISC-V port to allow for such bits, but that is being worked on as part of bringing up AndeStar RISC-V CPUs under the Linux kernel.

In addition to working on OpenMandriva Lx 4.0 as this distribution's next major release with its roots tracing back to the legendary Mandrake, its developers have also been working on clean ports of this Linux distribution to other CPU architectures.