The RISC-V architecture updates have landed in the Linux 5.15 kernel with more software features now being supported.

The RISC-V architecture code supports more functionality with the in-development Linux 5.14 kernel.

SiFive today is announcing the Performance P550 as the fastest RISC-V processor yet while also announcing the Performance P270 too.

The Linux kernel's RISC-V support continues picking up remaining features not yet wired up beyond the base architecture support. The latest is transparent hugepages (THP) to be supported for RISC-V with Linux 5.14.

Back in March during the announcement of Intel Foundry Services it was mentioned that SiFive and Intel were working together to allow RISC-V chips to be fabbed within Intel's facilities. Additionally, Intel Capital previously invested in SiFive during prior funding rounds. Now it turns out Intel is reportedly positioning to potentially acquire SiFive.

Announced last year was the HiFive Unmatched as the most compelling RISC-V development board to date. Following supply chain issues and everything else brought on by the pandemic, this very interesting RISC-V developer board is now shipping to customers.

From bringing up the PolarFire ICICLE SoC to adding support for KProbes, FORTIFY_SOURCE, and other new kernel features for the RISC-V architecture, the Linux 5.13 kernel changes are exciting for this open-source processor ISA.

SiFive's OpenFive business unit announced today they have completed their first tape out of a RISC-V processor core using TSMC's 5nm process.

Arguably the most interesting RISC-V board announced to date is SiFive's HiFive Unmatched with the FU740 RISC-V SoC that features four U74-MC cores and one S7 embedded core. The HiFive Unmatched also has 16GB of RAM, USB 3.2 Gen 1, one PCI Express x16 slot (operating at x8 speeds), an NVMe slot, and Gigabit Ethernet. The upstream kernel support for the HiFive Unmatched and the FU740 SoC continues.

It looks like the Linux 5.13 kernel will be supporting an interesting RISC-V feature this spring.

The Linux 5.12 merge window is drawing to a close this weekend while being sent in this morning were the RISC-V updates that tend to excite the free software enthusiasts.

It looks like the upcoming Linux 5.10 kernel cycle will be the first to bring initial support for UEFI booting on RISC-V hardware.

A few weeks back Alibaba announced the "XT910" as the fastest RISC-V processor featuring 16 cores and clock speeds up to 2.5GHz while being manufactured on a 12nm node. This by far beats most RISC-V hardware currently available and now at this week's Hot Chips conference the Chinese company is reporting that the XT910 is faster than an Arm Cortex-A73.

More kernel architecture features continue to be supported by the RISC-V code with Linux 5.9.

Following Linux's UEFI code getting cleaned up earlier this year in preparation for RISC-V support being added and then some early RISC-V UEFI patches, a more comprehensive set of patches for enabling UEFI support on RISC-V under Linux have been sent out.

The RISC-V architecture code in the Linux kernel continues seeing more improvements for running on real hardware and seeing other capabilities introduced.

The RISC-V architecture changes have been submitted for the Linux 5.7 kernel and includes early work on bringing up a new RISC-V dual-core SoC.

As we've been expecting to happen with the Linux EFI code being cleaned up before the introduction of a new architecture, the RISC-V patches have been posted for bringing up UEFI boot support.

RISC-V's Supervisor Binary Interface "SBI" is the interface between the platform-specific firmware and the running operating system or hypervisor for interacting with the supervisor execution environment in the higher privileged mode. The Linux kernel has been working to support a newer version of the SBI that is more extensible moving forward.

While still a draft standard, support for the RISC-V "V" Vector Extension support for the Linux kernel is currently being prepared.

Libre RISC-V, the project aiming to create an open-source accelerator that would run a Vulkan software renderer in being an "open-source GPU" aiming for just 25 FPS @ 720p or 5~6 GFLOPS, has managed to secure 300k EUR in grants for their work.

While there has been the Libre RISC-V community-driven effort to create a RISC-V graphics processor that basically amounts to a RISC-V core with vector extensions/improvements and running a Vulkan software implementation (though they are now reportedly eyeing POWER instead of RISC-V), Think Silicon has announced the first actual RISC-V ISA based 3D graphics processor.

The RISC-V kernel code has some interesting changes ready for Linux 5.5.

There is much greater performance potential out of RISC-V now with SiFive having announced the U8-Series.

Well, here is a surprise... The Libre RISC-V project that is trying to build an "open-source GPU" more along the lines as a Vulkan accelerator is looking at other options besides RISC-V. While RISC-V is royalty-free and open-source in nature, Luke Kenneth Casson Leighton is not content with the RISC-V Foundation and is evaluating the likes of POWER and MIPS.

To date there haven't been any really compelling RISC-V processors from a performance perspective but it's looking like we could soon be crossing that threshold.

In-step with more RISC-V hardware becoming available over time, the Linux kernel architecture support for RISC-V has continued maturing and with Linux 5.3 is in better shape.

Keith Packard has joined RISC-V company SiFive. Yes, the same Keith Packard that is the longest still active (though somewhat more dormant these days) X Window System developer who for many years had led much of the X11/X.Org efforts and worked for nearly a decade at Intel on their open-source Linux graphics driver stack before working for HP Labs and also a side-gig for Valve improving the Linux stack for VR.

The very ambitious project working on an open-source RISC-V architecture to serve as a Vulkan accelerator for 3D graphics secured a minor victory last week with receiving $50k EUR from the European Commission's Next Generation Internet initiative. They will be using these funds to allow for full-time engineering work and bounty-style tasks to work on this "100% libre RISC-V + 3D GPU chip for mobile devices."

If you want a SiFive SoC for the royalty-free, open-source RISC-V architecture it's now possible to pair it with graphics. Unfortunately, the graphics option is about as far from open-source as possible.