The State of RISC-V Hardware & Software In Early 2018

Palmer Dabbelt who maintains the RISC-V ports of GCC, Binutils, Linux, and glibc while working at RISC-V company SiFive spoke at FOSDEM 2018 this weekend about the software/hardware state of this royalty-free open-source CPU ISA.

Palmer's presentation covers the RISC-V instruction set, the origins of it, a brief comparison to other CPU architectures, and the Linux state.

As we have covered in the past with our many RISC-V articles, the support for this instruction set is largely upstream for the key components. The support was added to Binutils in 2.29, GCC in 7.1, and Glibc in 2.27. The Linux kernel RISC-V support was mainlined in Linux 4.15 but does not yet include any of the RISC-V hardware drivers.

Several major Linux distributions can bootstrap for RISC-V to varying degrees. Moving forward for the RISC-V architecture itself are new extensions for vectors and JITs as well as a Unix platform specification.

There is now a RISC-V public development board in form of the HiFive Unleashed, a 4+1 multi-core dev board using the SiFive FU540 SoC. This board has 8GB of DDR4 memory, Gigabit Ethernet, 32MB SPI flash, and microSD card. But before getting too excited, this first RISC-V development board will set you back $999 USD. Unfortunately well out of our reach for any Linux testing or benchmark comparisons unless we happen to receive a review sample.

Those wanting to learn more about the current state of RISC-V for early 2018 can see Palmer Dabbelt's presentation via the FOSDEM WebM recording or the PDF slides. Details on the HiFive Unleashed RISC-V development board via SiFive.com.