QEMU 5.1 Bringing Many CPU Improvements From Loongson To RISC-V To s390
Written by Michael Larabel in Virtualization on 16 July 2020 at 07:54 AM EDT. 18 Comments
VIRTUALIZATION --
QEMU 5.1-rc0 is available as the first step towards this next feature release of this important component to the Linux virtualization stack.

The QEMU 5.1-rc0 release marks the hard feature freeze for this next release. Weekly release candidates will continue until QEMU 5.1 is ready to ship around the middle of August. Among the many changes coming with QEMU 5.1 are:

- Support for the ARMv8.5 memory tagging feature and ARMv8.2 TTS2UXN, Raspberry Pi boards now support the USB controller, and other Arm improvements.

- Support for two Loongson 3A CPUs while improving the MIPS performance in general with this QEMU update.

- The ability to select POWER10 as a machine type on the IBM PowerPC front.

- Expanded support for AVR CPUs.

- A wide variety of RISC-V improvements including support for the SiFive E34, Ibex CPU, HiFive1 Rev B, OpenTitan, and a variety of RISC-V architectural additions.

- Support for protected virtualization / secure extension on IBM s390- with a z16 or Linux One III and using Linux 5.7+ with KVM.

- Various crypto improvements.

- Support for Zstd compression for QCOW2 images when using compress_type=zstd as a creation option.

The tentative list of QEMU 5.1 changes can be found in full via the project wiki. The latest stable and development releases of this open-source processor emulator can be downloaded at QEMU.org.
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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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