GCC Compiler Gets Tuned Up For MIPS' M51xx
Written by Michael Larabel in GNU on 22 July 2015 at 10:24 AM EDT. Add A Comment
GNU --
Within the latest GCC developer code is better support for Imagination's MIPS M51xx M-Class CPU family.

The MIPS M51xx is Imagination's entry-level Series 5 Warrior M-class CPU cores. The M51xx consists of two processor cores and are superset extensions of the MIPS microAptiv family, as explained on the Imagination Tech web-site. This MIPS Release5 Architecture processor family is designed for embedded applications ranging from IoT to automotive to wearables. The hardware was announced back in 2014.

Landing in SVN/Git this morning for GCC is scheduling support for the M51xx core family (with new -march options for m5100 and m5101)as well as support for the -march=interaptiv switch, which in turn maps to GCC's existing -mips32r2. These latest MIPS contributions to GCC were done by an Imagination Technologies engineer.
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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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