Linux Might Pursue x86_64 Micro-Architecture Feature Levels
Written by Michael Larabel in Hardware on 10 July 2020 at 04:16 PM EDT. 37 Comments
Stemming from the recent GNU glibc work on better handling modern CPU optimizations with newer instruction set extensions across Intel and AMD product families, the concept of x86-64 micro-architecture feature levels is being talked about by open-source/Linux developers.

The idea of these feature levels is breaking up the supported instructions beyond base x86_64 into that of what is supported at reasonable times by both Intel and AMD processors. While newer Intel/AMD CPUs generally support more instruction set extensions, there are other headaches involved in the current handling of x86_64 CPU capabilities considering the likes of modern Intel Atom CPUs only supporting a sub-set of the extensions supported by Core and Xeon CPUs, thus coming up with these reasonably sane feature levels is being talked about by Red Hat developers with input from Intel and AMD engineers.

With having these feature levels, it would allow better segregating different classes of x86_64 Intel/AMD CPUs and make it easier for Linux distributions to offer different levels of support or base requirements for their x86_64 images. The proposal was sent out today by Red Hat's Florian Weimer who is working on the glibc HWCAPS work as part of better allowing AMD Zen optimizations. For Red Hat's part, they have discussed raising the base CPU requirements in Fedora and planning to drop old CPU support in Red Hat Enterprise Linux 9. For RHEL9 it's been talked about of a possible base requirement of having AVX2 CPU support, but nothing appears set in stone yet.

These different feature levels for x86_64 at the current time are being proposed as:

Level A - CMPXCHG16B, LAHF/SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3. Barely going above the base x86_64 requirements.

Level B - Level A + AVX. The vintage of Intel Sandy Bridge and AMD Jaguar.

Level C - Level B + AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE. The point of roughly Intel Haswell era systems.

Level D - Level C + AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL. At this stage with the AVX-512 focus, just current Intel Xeon Scalable CPUs and Ice Lake.

Obviously moving forward into future CPU generations, additional levels could be easily introduced in building off this x86-64 level concept.

If this x86_64 level approach agreed upon and some consensus reached, GNU and LLVM could begin plumbing their library handling to first check for the most optimized feature level going back to the most basic / oldest until matching to the host CPU. From there when dynamically loading libraries and there being multiple builds of said library, it would attempt to load the best supported version in order to aim for the best performance. This level approach makes things much simpler considering otherwise the multitude of different CPU families/generations from both Intel and AMD to have a more reasonable subset of libraries/binaries to manage. Or these levels as mentioned earlier could be used for Linux distributions to up their base requirements beyond conventional x86_64.

It will be interesting to see where the discussion leads while for now the tentative idea is laid out on the mailing list across multiple different projects.
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Michael Larabel is the principal author of and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and automated benchmarking software. He can be followed via Twitter, LinkedIn, or contacted via

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