Many Intel/AMD x86 Changes Kick Off Linux 5.10 Development From Zen 3 To SERIALIZE
Written by Michael Larabel in Linux Kernel on 12 October 2020 at 07:11 AM EDT. 1 Comment
LINUX KERNEL --
On this first official day of breaking open Linux 5.10 for development with its merge window, quite a number of noteworthy Intel and AMD x86 processor changes have already been sent in for landing.

Some of the x86 material going in for Linux 5.10 we've previously discussed in recent weeks but here is a look at all of the x86-related changes sent in so far this morning for the Linux 5.10 merge window:

The x86/pasid updates bring initial support for sharing virtual addresses between the CPU and devices which doesn't need pinning of pages for DMA anymore. Process Address Space Identifiers (PASID) and ENQCMD/ENQCMDS instruction set extensions for Intel Sapphire Rapids are now supported. This is part of the kernel starting to leverage the Intel Data Streaming Accelerator coming with those Xeon CPUs due out in about one year's time.

Meanwhile the x86/cpu changes have several interesting features from different vendors. On the AMD side there is SME hardware-enforced cache coherency. On the Intel side there is now initial usage of the Intel SERIALIZE instruction to further put a stop to speculative execution issues. SERIALIZE support is coming to Alder Lake and Sapphire Rapids next year. Also in this pull is SLDT/STR emulation for helping some Windows games with Wine for users experiencing crashes on UMIP-enabled systems. Outside of Intel and AMD in the x86space, there is Zhaoxin 7-Series Centaur CPU support underway.

On the RAS (Reliability, Availability and Serviceability) front there is new AMD hardware enablement... AMD Zen 3, well, for the upcoming AMD EPYC 7003 "Milan" processors. The EDAC (Error Detection And Correction) changes also have work for "new AMD CPUs", again appearing to be for the Zen 3 EPYC processors with Family 19h 20h through 2Fh models.

Meanwhile x86/cache adds support for controlling per-thread memory bandwidth (MBA / Memory Bandwidth Allocation) rather than per-core as a feature appearing to come for future Intel Xeon processors. On the x86/platform front there is initial work on HPE (SGI) UV5 support.

Also new are FSGSBASE cleanups after the initial FSGSBASE implementation was finally mainlined back during the Linux 5.9 cycle.

Overall, a fun start to the Linux 5.10 merge window... Stay tuned for more features landing over the coming days and once the release candidates begin will be our usual kernel benchmarking.
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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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