MIPS Gets Spectre Variant Two Mitigation In LLVM
Written by Michael Larabel in LLVM on 21 February 2018 at 05:38 AM EST. Add A Comment
LLVM --
Besides x86_64, we have seen Spectre mitigation work happen recently for ARM, POWER, and IBM s390, but no prominent MIPS activity to report until now.

The Spectre Variant Two vulnerability affects P5600 and P6600 chips while as part of their mitigation strategy is a new LLVM patch that was just merged and introduces a -mindirect-jump=hazard switch. This is different from the Variant Two mitigation technique on x86 of Retpolines.

For mitigating Spectre V2, using the hazard barrier instructions are recommended to stop the instruction stream until defined hazards are cleared, which does not involve any speculation by the processor. These instructions are supported by the MIPS R2 ISA and later.

The developers found that using the -mindirect-jump=hazard as their Spectre Variant Two mitigation yields around a ~10% performance hit, at least when testing with the LLVM test suite, but some workloads are likely to see a much higher impact.

More details via this commit to mainline LLVM. As of writing I have yet to see any similar MIPS patches for the GCC compiler.
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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 10,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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