LLVM Clang 14 Begins Landing Intel AVX-512 FP16 Support
Written by Michael Larabel in LLVM on 16 August 2021 at 02:33 PM EDT. 8 Comments
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Last month Intel began posting the developer documentation around AVX-512 FP16 support coming with Sapphire Rapids and initially accompanied by GCC compiler patches along with LLVM/Clang. While that GNU Compiler Collection support around AVX-512 FP16 has yet to be merged, the LLVM Clang support for this next iteration of AVX-512 has begun landing.

Next-generation Intel Xeon Scalable "Sapphire Rapids" will support AVX-512 FP16 with full-speed handling of denormal FP16 values - not to be confused with AVX-512 BF16 (BFloat16) found on Cooper Lake. AVX-512 FP16 should help with deep learning models and other cases where FP32 isn't necessary.

The LLVM patches around enabling the new AVX512FP16 instructions have been merged to LLVM Git along and the new -mavx512fp16 option.

Further AVX-512 FP16 work for LLVM is still pending but that initial enablement is now in Git. This missed making it into LLVM 13.0 that recently branched from the Git main branch, but puts it in line for having baked support in LLVM 14.0 that will release in early 2022. Similarly, the GCC patches should be merged in time for GCC 12 due out roughly around the similar time next year.

Intel Sapphire Rapids processors will be ramping in Q2'2022 so these new compilers will be out by then with AVX-512 FP16, Advanced Matrix Extensions, and other new instructions supported by Sapphire Rapids. Normally Intel is more punctual in getting their compiler support out even earlier while for this time at least they will be in released compilers ahead of launch day, just not a year or more in advance as sometimes has been the case.
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