Intel Tightens Up Its AVX-512 Behavior For The LLVM Clang 10 Compiler
Written by Michael Larabel in LLVM on 12 September 2019 at 07:27 AM EDT. 2 Comments
LLVM --
Intel engineer Craig Topper who frequently contributes the new Intel CPU support to LLVM/Clang has made an AVX-512 behavioral change for next spring's LLVM Clang 10 release.

When targeting Skylake-AVX512, Icelake-Client, Icelake-Server, Cascadelake, or Cooperlake with the LLVM Clang compiler where AVX-512 is supported, it will now default to preferring the 256-bit vector width rather than 512-bit with AVX-512. Unless 512-bit intrinsics are used in the source code, 512-bit ZMM registers will not be used since those operations lead to most processors running at a lower frequency state. On current generation processors, the performance gains of AVX-512 can often times be negated due to the AVX-512 frequency hits.

GCC and other compilers including Intel's own ICC have already implied the "-mprefer-vector-width=256" behavior when using AVX-512 while now LLVM/Clang 10.0 is as well. The "-mprefer-vector-width" option can be used in existing compiler releases for setting the preferred vector width for vectorizers.

The change landed ahead of the first LLVM release due out in early 2020.
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