Intel GCC Patches + PRM Update Adds SERIALIZE Instruction, Confirm Atom+Core Hybrid CPUs
Written by Michael Larabel in Intel on 1 April 2020 at 06:48 AM EDT. 7 Comments
INTEL --
Intel has seemingly just updated their public programming reference manual as well as sending out some new patches to the GCC compiler for supporting new instructions on yet-to-be-released CPUs.

Hitting the mailing list early this morning was support for TSXLDTRK. TSXLDTRK is Intel TSX Suspend Load Address Tracking and is confirmed as coming with Sapphire Rapids / Golden Cove. With that is the XSUSLDTRK to suspend tracking load addresses and XRESLDTRK so that software developers can choose the memory accesses that do not need to be tracked by a TSX (Transactional Synchronization Extensions) read set.

Another new instruction sent out in patch form for GCC this morning is SERIALIZE. The SERIALIZE instruction is set for Alder Lake and Sapphire Rapids. SERIALIZE will ensure all flags/register/memory modifications are complete and draining all buffered writes to memory before executing the next instruction. This serializing of the instruction fetch and execution would seemingly be a sizable performance penalty but we'll see about Intel's intended usage of it or other architecture improvements with Golden Cove to make SERIALIZE less costly.

Due to GCC 10 stable coming out in a matter of weeks, these new features for Intel Golden Cove cores won't be landing until GCC 11. But at least with capable CPUs now expected until 2021, GCC 11 should be out next year before such CPUs surface.


The other exciting piece of information from Intel's new PRM update is confirmation of hybrid CPU designs in the future. There is now a HYBRID bit on future CPUs to indicate core types whether it be an Intel Atom or Intel Core (plus some reserved bits for future expansion). There have been rumors floating around of Intel pursuing a CPU design similar to Arm's big.LITTLE and this HYBRID feature would seem to reinforce that such processors may be coming. Rumors pointed to Alder Lake having the mix of big and little cores and the timing of this PRM update with HYBRID would reinforce that as something that Intel is planning.
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