L3 Cache Partitioning Coming For The Intel DRM Driver
Written by Michael Larabel in Intel on 7 September 2015 at 09:10 AM EDT. Add A Comment
Francisco Jerez has been tackling L3 cache partitioning for the Intel DRM driver, which will yield some interesting possibilities moving forward.

This L3 cache partitioning code will be useful for supporting compute shaders with shared variables, improved performance of scratch access, atomic counters, and images, and will be possible for other advantages down the road.

Those interested can see this Mesa mailing list post.

In the L3 atomics patch Francisco commented, "Improves performance of the arb_shader_image_load_store-atomicity piglit test by over 25x (which isn't a real benchmark it's just heavy on atomics -- the improvement in a microbenchmark I wrote a while ago seemed to be even greater). The drawback is one needs to be extra-careful not to hang the GPU (in fact the whole system)."
Related News
About The Author
Author picture

Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

Popular News This Week