GCC Getting Wired Up For Intel's Key Locker, UINTR, HRESET, AVX-VNNI
Written by Michael Larabel in Intel on 14 October 2020 at 06:21 AM EDT. Add A Comment
INTEL --
Following this month's Intel programming reference manual update disclosing a number of new instruction set extensions, Intel's compiler engineers have gone public with patches for implementing some of these forthcoming CPU features.

The latest GCC compiler-side work around new instruction set extensions coming to future generations of Intel CPUs include:

Key Locker Support - Intel has already been adding Key Locker support to other parts of the GNU toolchain and the LLVM support also landed while the GCC support should be here for GCC 11. Key Locker works with Tiger Lake and allows for encrypting/decrypting data without a (raw) AES key but rather relies upon a key handle that is in place until revoked by the system. The intent of Intel Key Locker is trying to prevent actual AES keys being obtained from rogue attackers.

UINTR - The new feature for user interrupts as new events for software running at CPL 3 and without having to change the segmentation state.

HRESET - The instruction provides a hint to the processor to selectively reset the prediction history of that CPU core. The initial usage around this is for the Intel EHFI / Enhanced Hardware Feedback Interface as a means of providing guidance to the kernel scheduler over optimal task placement of workloads among the available logical processors based on whether wanting maximum performance or power savings.

AVX-VNNI - The equivalent to AVX512-VNNI with VEX encoding for Vector Neural Network Instructions outside the AVX512 context.

Those are the latest Intel patches for GCC. The work should presumably be squared away in time for GCC 11 due out around March~April of next year.
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