Coreboot Improvements For FU540 Land Following SiFive's Open-Source Boot Code
Written by Michael Larabel in Coreboot on 14 September 2018 at 07:35 AM EDT. 8 Comments
COREBOOT --
Last week SiFive published their HiFive Unleashed open-source boot-loader code for this first RISC-V SoC on their Linux-friendly development board. This code being open-sourced has already helped improve the support for the FU540 SoC within Coreboot.

The code open-sourced last week by SiFive allows for a fully open-source boot process after this first RISC-V developer board received some criticism for some of its initialization code being closed-source, namely around the SDRAM start-up code.


Prior to this open-source code drop, even in the Coreboot community it was commented that HiFive wasn't more open than the average ARM SoC. But now that there is this open-source reference code, the Coreboot support for SiFive's HiFive Unleashed development board can be improved.

As of this morning, the Coreboot FU540 port can now initialize the SDRAM based upon this open-source boot-loader code. The Coreboot port for this board has been a work in progress since landing back in April.

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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 10,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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