Arm Outlines More Neoverse N2 + Neoverse V1 Platform Details
Written by Michael Larabel in Arm on 27 April 2021 at 08:52 AM EDT. 21 Comments
ARM --
Arm published today a set of blog posts outlining more power/performance and feature details of their forthcoming Neoverse N2 and Neoverse V1 platforms.

As announced last September, Arm's Neoverse V1 platform is for delivering the highest performance from any Arm-designed core. The Neoverse V1 while based on the N1 has a "radical redesign of the CPU microarchitecture". The Neoverse V1 platform supports multi-chiplet and multi-socket solutions and can support DDR5/HBM3 memory, PCI Express 5.0, and CXL 2.0 attached memory and coherent accelerators.

Among the architectural features the Neoverse V1 has on top of the N1 are Int8 MatMul, BFloat16, speculation barriers, deep persistence, Scalable Vector Extensions (SVE), enhanced cryptography, RAS extensions, nested virtualization, pointer authentication, and more.

The V1 also has a new micro-opcode cache, the bandwidth has doubled to 32 bytes/cycle, greater load and store buffer sizes, and better data pre-fetch algorithms.

On top of performance features being added, the Arm Neoverse V1 also has new power management features. The power features are maximum power mitigation mechanism (MPMM) for ensuring optimal frequencies are achieved in high core count configurations and Dispatch Thorttling (DT) for more aggressive thermal throttling.

As for some V1 performance expectations, "The performance uplifts are sorted from least to maximum with an aggregate score showing ~48% IPC improvement over Neoverse N1 (very close to the 50% SPEC CPU 2006 estimated score). The steep rise of relative performance of Neoverse V1 over N1 is for workloads that benefit from the doubling of the vector datapath and deployment of SVE (eg. Crypto, packet processing and others that deploy SIMD). On the right graph we rank SVE workload performance for Neoverse V1 over NEON performance for N1, showing an impressive 60% to 300% improvement in performance due to SVE vector datapath."


More details on the Neoverse V1 power/performance design details via this blog post.

Arm also further detailed today Neoverse N2 platform details as Arm's first ARMv9 infrastructure CPU. With ARMv9 the N2 has SVE2, new crypto instructions, new trace capabilities, and more. Neoverse N2 silicon is expected to begin sampling to their partners by the end of the calendar year.
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