Optimized C3 Entry Handling For AMD CPUs Queued For Linux 5.15

The work I initially wrote about last week for AMD optimizing their C3 entry handling to avoid an unnecessary cache flush will now be picked up for the upcoming Linux 5.15 kernel cycle.

As explained in the prior article, this optimization around entry to the ACPI C3 sleep state is already applied for Intel, Zhaoxin, and Centaur processors on Linux. Unfortunately, it's just AMD CPUs are late to the party with the kernel code not having marked them as safe for this optimization until an AMD engineer submitted a patch last week.

When a CPU core enters the C3 power sleep state, the default behavior to ensure cache coherence is to flush the cache even if that cache is shared with other CPU cores not currently sleeping. Thus AMD's Deepak Sharma submitted a patch last week to allow the optimization unconditionally for all AMD CPUs, "AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly."

That patch has now been picked up as part of the ACPI material being collected for the Linux 5.15 merge window. That next cycle is expected to kick off next week pending the release of Linux 5.14 this weekend and in turn will debut as stable this autumn. This basic optimization is overdue, but at least the few lines of code patch is now on the way to being merged.