Intel Architecture Day 2021 & The Linux State
Written by Michael Larabel in Processors on 19 August 2021. Page 6 of 6. 29 Comments

Xe HPC and Ponte Vecchio also was covered at this year's Architecture Day.

Ponte Vecchio has more than 100 billion transistors, 47 active tiles, and makes use of five different process nodes. Ponte Vecchio has eight Xe cores per compute tile, 4MB of L1 cache per tile, and is built on a TSMC N5 process for the compute tiles and leverages their Foveros technology. Ponte Vecchio's base tile meanwhile is built on an Intel 7 process and has a 144MB L2 cache with HBM2e and supports PCI Express Gen5.

One of the new interesting technologies for Xe HPC is Xe Link as a high-speed coherent unified fabric. Xe Link supports up to eight fully connected GPUs through an embedded switch.

Ponte Vecchio in its early (A0 silicon) form is seeing greater than 45 TFLOPS of FP32 throughput, greater than 5 TBps of memory fabric bandwidth, and greater than 2 TBps of connectivity bandwidth. Intel is planning on having Ponte Vecchio ready for HPC and AI markets in 2022.

As with the rest of Intel's graphics landscape, Xe HPC continues to be supported under Linux via a fully open-source driver stack with all those mainline components still coming together for Xe HPC. In user-space there is Intel's excellent oneAPI open-source software stack that continues seeing significant industry interest and adoption.

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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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