Skylake Server Scheduler Model Updated In LLVM 6.0 Along With Other Intel CPU Updates

Written by Michael Larabel in LLVM on 10 December 2017 at 01:03 PM EST. Add A Comment
The x86 scheduler model for Skylake AVX-512-enabled servers has been updated ahead of the LLVM 6.0 feature freeze next month.

A number of commits landed in LLVM Git/SVN a short time ago for further tuning the Skylake server scheduler model as well as adding some supported instructions previously not included as part of this model.

While the Skylake Server scheduler model appears to have received a bulk of the work today, the Sandybridge / Haswell / Broadwell scheduler models also received a few updates as well for optimized instruction scheduling.

The recent activity can be seen from this GitHub query.

I'll be running some fresh Intel x86 CPU tests of LLVM 5.0 vs. 6.0 SVN soon for seeing how the performance is looking with this compiler infrastructure update that will be released as stable in March of 2018.

In other LLVM work earlier in the day, the AMD Zen "znver1" scheduler model is also now tagged as being complete. Likewise, I'll be running some new AMD compiler benchmarks soon.
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