SiFive Begins Adding RISC-V "Bullet" Microarchitecture Code To LLVM
The initial work is on the scheduler being added for the RISC-V Bullet. The initial scheduler is in place for the RISC-V Bullet microarchitecture and bullet-rv32 / bullet-rv64 naming.
The scheduler code does reveal some key bits such as the SiFive Bullet has dual pipelines. The first pipeline handles memory / integer ALU / vector operations while the second pipeline is for integer ALU / control flow / integer multiply / divide / floating point computations. Bullet supports dispatching two micro-ops per cycle. This Bullet support was worked on by two SiFive engineers.
But as far as other details go on SiFive's RISC-V Bullet microarchitecture, this is the first appearance of it within LLVM (or GCC) and search results haven't been of any help turning up any other relevant references for this seemingly yet-to-be-launched RISC-V microarchitecture update.