NVIDIA Publishes Reference Documentation For Volta's Display Hardware

NVIDIA has today released the display hardware documentation for "GV100" Volta graphics hardware.

Before getting too excited, this is strictly about the display hardware and not about the 3D engine, etc. And by "documentation", it's about 6,000 line header file of the registers for the Volta display hardware. For example:

#define NV_PDISP_FE 0x00615FFF:0x00610000 /* RW--D */
#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */
#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */
#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
#define NV_PDISP_EXCEPT_CHN_NUM_WIN(i) (1+(i)) /* */
#define NV_PDISP_EXCEPT_CHN_NUM_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_CLASSES 0x00610000 /* R--4R */
#define NV_PDISP_FE_CLASSES_HW_REV 3:0 /* R--UF */
#define NV_PDISP_FE_CLASSES_API_REV 7:4 /* R--UF */
#define NV_PDISP_FE_CLASSES_CLASS_REV 15:8 /* R--UF */
#define NV_PDISP_FE_CLASSES_CLASS_ID 31:16 /* R--UF */
#define NV_PDISP_FE_CLASSES_0 3278897936 /* */
#define NV_PDISP_FE_INST_MEM0 0x00610010 /* RW-4R */
#define NV_PDISP_FE_INST_MEM0_TARGET 1:0 /* RWIVF */
#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_INIT 0x00000001 /* RWI-V */
#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_NVM 0x00000001 /* RW--V */
#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_PCI 0x00000002 /* RW--V */
#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */
#define NV_PDISP_FE_INST_MEM0_STATUS 3:3 /* RWIVF */
#define NV_PDISP_FE_INST_MEM0_STATUS_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_INST_MEM0_STATUS_INVALID 0x00000000 /* RW--V */
#define NV_PDISP_FE_INST_MEM0_STATUS_VALID 0x00000001 /* RW--V */
#define NV_PDISP_FE_INST_MEM1 0x00610014 /* RW-4R */
#define NV_PDISP_FE_INST_MEM1_ADDR 30:0 /* RWIUF */
#define NV_PDISP_FE_INST_MEM1_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_IP_VER 0x00610018 /* R--4R */
#define NV_PDISP_FE_IP_VER_DEV 7:0 /* R-IVF */
#define NV_PDISP_FE_IP_VER_DEV_INIT 0x00000000 /* R-I-V */

So it's a far cry from the graphics hardware documentation that Intel and AMD routinely publish for their hardware where they document the registers and also provide proper descriptions, etc, but at least it's something. This may also be enough for the Nouveau developers to get their DRM/KMS driver working with kernel mode-setting for Volta hardware, assuming they have GV100 hardware for access -- NVIDIA in recent years at least has been good with seeding some hardware to these open-source Linux driver developers. But getting 3D acceleration going is an entirely different battle, not to mention the need now also waiting for NVIDIA to release signed firmware images that are necessary since Maxwell for hardware initialization.

With Volta hardware not being in the hands of many, it's also quite punctual compared to the small code/documentation drops we have seen from NVIDIA in the past often being years later.

Any developers wanting this 6,000 line header file for the GV100 display hardware can find it here.