Google Worked On A New Aspeed Control Driver For Linux 5.2

Aspeed BMCs have seen a lot of mainline Linux kernel driver activity from a recent Aspeed video engine driver to an AST2500 SoC DRM driver queued for Linux 5.2 and now also joining that is the Aspeed P2A CTRL driver.

This Aspeed P2A control driver was worked on by Google developers and is for dealing with the AST2400/AST2500 where supporting a PCI-to-AHB MMIO bridge for leeting the system read/write to the BMC's physical address space as part of features like sending files to the BMC. The 500+ lines of code for the ASPEED_PTA_CTRL "aspeed-pta-ctrl" driver is used for managing this interface.

The driver by Google's Patrick Venture was added to the char-misc-next area ahead of Linux 5.2. The commit explains:

The host may use this to send down a firmware image by staging data at a specific memory address, and in a coordinated effort with the BMC's software stack and kernel, transmit the bytes.

This driver enables the BMC to unlock the PCI bridge on demand, and configure it via ioctl to allow the host to write bytes to an agreed upon location. In the primary use-case, the region to use is known apriori on the BMC, and the host requests this information. Once this request is received, the BMC's software stack will enable the bridge and the region and then using some software flow control (possibly via IPMI packets), copy the bytes down. Once the process is complete, the BMC will disable the bridge and unset any region involved.

The default behavior of this bridge when present is: enabled and all regions marked read-write. This driver will fix the regions to be read-only and then disable the bridge entirely.

The memory regions protected are:

* BMC flash MMIO window
* System flash MMIO windows
* SOC IO (peripheral MMIO)
* DRAM

The DRAM region itself is all of DRAM and cannot be further specified. Once the PCI bridge is enabled, the host can read all of DRAM, and if the DRAM section is write-enabled, then it can write to all of it.