RISC-V Gets Sv57-Based Virtual Memory, Other Improvements For Linux 5.18

The RISC-V CPU architecture updates have landed for the in-development Linux 5.18 kernel.

Notable with the RISC-V additions for Linux 5.18 is sv57 support for 5-level page tables. It was just with the prior kernel that sv48 was added for 4-level page tables on RISC-V while this new kernel brings it up to 57-bit page-based virtual memory support for allowing RISC-V systems of the future with even greater memory capacities.

Last year with Linux 5.13 the Microchip PolarFire was added to the mainline kernel while Linux 5.18 is further improving that target. With Linux 5.18 there are improvements for the PolarFire SoC and ICICLE development board that in turn now allow the upstream RISC-V kernel build to run gracefully on the hardware without any extra modifications.

RISC-V with Linux 5.18 also has a new memmove() implementation. The prior memmove() did not properly check memory alignment and could cause the kernel to crash on some systems while elsewhere would just be a sub-optimal performant experience.

Also notable with RISC-V for Linux 5.18 are supporting additional extensions for a "much more useful perf implementation" for those wanting to use the Linux kernel's perf subsystem on RISC-V.

Last but certainly not least is Restartable Sequences "RSEQ" support on RISC-V for what can be a performance win when using the new interfaces.

The RISC-V based SiFive HiFive Unmatched

The full list of RISC-V changes for Linux 5.18 via this Git merge.