Libre-SOC Test ASIC Going To Fabrication, Using TSMC 180nm Process

Libre-SOC that started out as Libre RISC-V in aspiring to be an open-source software/hardware Vulkan accelerator but then renamed to Libre-SOC after changing over to the OpenPOWER architecture is now seeing test fabrication done using TSMC's 180nm process.

This test ASIC is being fabbed thanks to Imec's MPW Shuttle Service, Libre-SOC is all about being a hybrid CPU/GPU that's 100% open-source but obviously not the fastest compared to today's graphics processors. For achieving the graphics acceleration the plan is basically to use the likes of Mesa's software OpenGL/Vulkan implementations atop this Power-based chip.

This ambitious open-source hardware project has been able to move forward thanks to grants from the likes of NLNet and cooperation from Chips4Makers and Sorbonne Université.

Libre-SOC in its current form implements a fixed-point subset of OpenPOWER ISA v3.0B. The ASIC at present has 130k gates and measures in at 5.5 x 5.9 mm2.

Multiple test fabrications using Imec's MPW Shuttle Service on a TSMC 180nm process are expected before this chip is possibly ready for use as a hybrid CPU-VPU-GPU. The next test ASIC is expected to include a draft version of Cray-style vector extensions.

More details on this achievement via the OpenPOWER blog.