LLVM Compiler Finally Gets A Tuned Scheduler Model For Intel Alder Lake P

While Intel is normally fast at contributing improvements for new hardware to the open-source GCC and LLVM/Clang compilers, just today and ahead of the approaching Raptor Lake launch has a proper scheduler model finally been added for existing Alder Lake P processors.

An Alder Lake P scheduler model has been added to LLVM Git for LLVM 16.0. This Intel-contributed change adds the proper instruction costs for the scheduler model rather than up to this point just copying the model used since Skylake.

The model provides the compiler with more details on the micro-architecture and the resource tables can provide the latency and cost for each instruction type. The model is useful when tuning the compiler's generated binaries for the given CPU and the compiler being able to make more informed decisions based on that model.

This Alder Lake P scheduler model was generated in part via the LLVM "schedtool" also being worked on by Intel. The schedtool aims to help generate x86 schedule models automatically to make it less time consuming and eliminating the possibility of errors or inaccurate entries. That LLVM schedtool is still a work-in-progress but was good enough to get this Alder Lake P model generated.

The fifteen thousand lines of new code for the Intel Alder Lake P schedule model was added as part of this commit merged today to LLVM Git. It will be fun to run some fresh LLVM Clang compiler benchmarks with "-march=native" tuning to see if this new model is able to provide a quantifiable improvement for existing Intel Core 12th Gen CPUs.