LLVM 17 Adds New ISA Support For Intel Arrow Lake S & Lunar Lake
Following GCC recently adding new x86 instructions for Intel Arrow Lake and Lunar Lake, the LLVM 17 open-source compiler has now received similar treatment.
Intel's compiler experts have begun upstreaming Arrow Lake and Lunar Lake support well ahead of the processor launches so that by the time these future generation CPUs actually ship the compilers will be out as stable and this support will have already worked their way into the compilers used by modern Linux distributions at the time.
Merged overnight to the LLVM 17 Git codebase is enabling AVX-VNNI-INT16, SHA512, SM3, and SM4 instructions.
The LLVM patches meanwhile have yet to land for introducing the new "arrowlake" and "lunarlake" targets for the LLVM Clang compiler, but that work shouldn't be far behind with the new ISA additions now merged.
LLVM 17.0 stable should be out in the usual September~October timeframe.
Intel's compiler experts have begun upstreaming Arrow Lake and Lunar Lake support well ahead of the processor launches so that by the time these future generation CPUs actually ship the compilers will be out as stable and this support will have already worked their way into the compilers used by modern Linux distributions at the time.
Merged overnight to the LLVM 17 Git codebase is enabling AVX-VNNI-INT16, SHA512, SM3, and SM4 instructions.
The LLVM patches meanwhile have yet to land for introducing the new "arrowlake" and "lunarlake" targets for the LLVM Clang compiler, but that work shouldn't be far behind with the new ISA additions now merged.
LLVM 17.0 stable should be out in the usual September~October timeframe.
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