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Intel Software Defined Silicon Planned For Integration In Linux 5.18
Last September I was the first to draw attention to Intel's patches for Software Defined Silicon for enabling extra licensed hardware features on Linux. The kernel driver is about handling the necessary cryptographic-based activation of "additional silicon features" but the infrastructure is rather generic and doesn't outline to what extent Intel is planning to now make CPU features available as an additional upgrade/license.
After bringing attention to the patches, the folks over at The Register then asked Intel about SDSi. Intel responded by saying, "We’re not going into a lot of details about Software Defined Silicon at this time. As you know, Intel regularly submits code to the Linux Kernel that could be used in future products. And that’s what happened in this case. If we plan to implement these updates in future products we will provide a deeper explanation of how they are implemented at that time."
But since then Intel has continued working on the SDSi Linux code with this new driver for activating additional CPU features. Now it turns out they are working to get the Software Defined Silicon support into the next version of the Linux kernel.
Following the v6 patches, the x86 platform drivers subsystem maintainer commented that he is planning to go through his review of the driver next week with plans to get it ready for mainlining: "Assuming no major issues are found, the plan definitely is to get this in before the 5.18 merge window."
So it does look like SDSi is moving along and barring any last minute issues will be found in Linux 5.18. The v5.18 merge window kicks off at the end of March while the stable kernel will be here around the end of May.
Based on this rather rapid timing since seeing the patches quickly revised through Q4 and now aligning for Linux 5.18, it's possible SDSi may make its debut for Xeon Scalable "Sapphire Rapids" or perhaps more likely the successor to the Rocket Lake Xeon W-1300 / E-2300 series, a.k.a. the Alder Lake Xeon chips... There have been various rumors recently regarding Alder Lake Xeon chips and would make more sense if Intel is going to make use of SDSi there with their entry-level server/workstation chips rather than with high-end Xeon Scalable processors. In any case with there some interest/emphasis on having SDSi ready for Linux 5.18, it's presumably to prepare for chips coming this year and not 2023~2024.
One possibility that comes to mind is Intel gating AVX-512 with Alder Lake Xeon chips as an SDSi upgrade feature. We know Alder Lake's P cores have AVX-512 when the E cores are disabled and enabling AVX-512 from the BIOS, but more recently motherboard vendors have begun outright removing that functionality from their Alder Lake S consumer desktop motherboards. It will be interesting to see how AVX-512 is handled with Alder Lake Xeon processors if there is that functionality enabled -- or perhaps that is where Software Defined Silicon makes its debut. By gating AVX-512 behind SDSi would also potentially free up some software complexities around dealing with AVX-512 only being available on the P cores with hybrid processor designs. As of my last check, the Linux kernel doesn't have the logic for task placement where AVX-512 execution can only happen from select threads/cores / automatic migration when finding an instruction not supported by the current core, so short of that being wired up it would be reliant upon the user/administrator (or some daemon) pinning AVX-512 tasks to the P cores. If a user is going through the SDSi activation steps (and running a new enough kernel) and paying extra to get AVX-512, presumably then the user/administrator is aware of such limitations and can then ensure the AVX-512 workloads will be properly setup for their software environment.
Anyways, long story short, Intel Software Defined Silicon is expected to land with Linux 5.18. Intel has not offered any public announcements or guidance yet how they plan to commercialize around SDSi but will be interesting to see... While just speculation for now, given the current state with Alder Lake on the consumer side with AVX-512 in fact being present for P cores, I can't help but wonder if their upcoming entry-level Xeon chips could have AVX-512 for P cores as an opt-in/upgrade feature. We'll see.