More Sandy Bridge Scheduling Updates For LLVM

Written by Michael Larabel in Intel on 13 August 2017 at 10:07 AM EDT. 5 Comments
Intel engineers continue tuning the Sandy Bridge scheduler information within the LLVM compiler infrastructure.

Last month Intel developers submitted new scheduler data for Sandy Bridge CPUs. While Sandy Bridge is rather old at this point, they intend as well to revamp the LLVM scheduler information for newer generations of Intel CPUs too. In particular, updates are expected for Ivy Bridge, Haswell, Broadwell, Skylake, and Skylake-X.

Landing today in LLVM Git/SVN is additional tuning for the new Sandy Bridge "SNB" scheduler data. The commit explains:
[X86][SandyBridge] Additional updates to the SNB instructions scheduling information

This is a continuation patch for commit r307529 which completely replaces the scheduling information for the SandyBridge architecture target by modifying the file located under the X86 Target (see also

In this patch we added the scheduling information of additional SNB instructions that were missing from the patch commit r307529, fixed the scheduling of several resource groups that include only port0 instead of port05 (i.e., port0 OR port5) and fixed several incorrect instructions' scheduling in the r307529 commit.

The patch also includes the X87 instructions which were missing in previous patch commit r307529 as reported in bugzilla bug 34080.

I'll try to get some fresh LLVM Clang benchmarks on Sandy Bridge done in the days ahead.
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