Intel Linux Graphics Driver Merges "Major Improvement" For Xe3 With VRT Support

Variable Register Thread is a new feature of Xe3 and is described within the Intel Mesa merge request as:
"This MR adds support for VRT which is one of the major improvements introduced in the Xe3 ISA. In short it allows EU threads to use a variable number of registers that can be specified by the driver in a pipelined fashion for each shader stage. While using this feature up to 256 GRF registers can be used per thread at the cost of reducing the number of threads that can execute concurrently in the same EU -- Or conversely, a number of registers lower than 128 GRF can be allocated per thread, which allows the EU to execute a larger number of threads concurrently.
This has two primary benefits: On the one hand the amount of spilling is vastly reduced (spills drop by ~95% and fills by ~48% on shader-db, spills drop by ~86% and fills by ~76% on fossil-db) which is expected to reduce bandwidth consumption and improve performance at run-time, and OTOH the ability to compile a SIMD32 variant of most shaders allows for a more compile time-efficient heuristic to be used for SIMD width selection."
That sounds quite exciting on its own especially with the sharply reduced register spilling. For some insight as to the impact with Xe3 VRT, the merge request ended with noting:
"This reduces the compilation time for a whole run of shader-db by ~15%, and the runtime of fossil-db by ~20% (both figures on Xe3, the spill and fill count improvements reported above are still approximately accurate)."
Around a 15% reduction in compiling the whole mess of shaders within shader-db and then around a 30% runtime improvement for all the shader execution tests within Fossil-DB is very significant.
The code was merged on Wednesday in time for making the Mesa 25.0 cut-off so that this Xe3 work will begin shipping later this quarter. It's great seeing Intel Linux driver engineers working quite eagerly on the Xe3 graphics support with the initial focus being on for the integrated graphics to be found with next-gen Core Ultra "Panther Lake" processors.
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