Intel Icelake Support Lands In GCC 8
The -march=icelake switch is what's now supported by GCC if desiring an optimized build catering towards this Intel CPU successor to Cannonlake. The Icelake target implies MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, VX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, and VAES instruction set extensions.
Icelake continues with the AVX-512 extensions but also adds GFNI support as well as Vector Neural Network Instructions (VNNI).
Icelake CPUs are expected to appear likely in 2019. Besides getting the compiler toolchain changes in place, Intel open-source developers have also already been posting open-source patches for bringing up the "Gen 11" graphics of Icelake, among other Linux kernel enablement work.