New Intel Diamond Rapids Patch For GCC Confirms AVX10.2-512, APX & Other ISA Features

Intel software engineers have been very busy recently with upstreaming various elements of support into the Linux kernel, open-source compilers and more for the next-generation Xeon Diamond Rapids processors. Following the recent GCC prep patches for Diamond Rapids to work on the ISA additions around AMX-AVX512, AMX-FP8, AMX-FP32, and others, a new patch was posted today for actually exposing the "-march=diamondrapids" compiler target and in turn confirming all of the new ISA capabilities.

Intel Diamond Rapids is looking quite exciting on the CPU ISA front. In addition to the many Advanced Matrix Extensions (AMX) additions coming with Diamond Rapids, we now have solid confirmation with today's patch that Diamond Rapids will be supporting AVX10.2-512 as the latest of AVX10.

Plus this Friday patch confirms Diamond Rapids as having the previously disclosed Advanced Performance Extensions (APX) functionality.

AVX10 and APX were widely assumed for Diamond Rapids while this GNU Compiler Collection patch today confirms it plus the other ISA features.

The documentation portion of the patch notes:

"Intel Diamond Rapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB, MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16, PREFETCHI, AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512, AMX-FP8, AMX-TF32, AMX-TRANSPOSE, MOVRS, AMX-MOVRS and USER_MSR instruction set support."

Or the new additions with Diamond Rapids compared to current Granite Rapids comes down to AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512, AMX-FP8, AMX-TF32, AMX-TRANSPOSE, MOVRS, AMX-MOVRS, and USER_MSR.

Great seeing Intel with their very timely support for enabling new CPU ISA features and the CPU family "-march=" targets for both GCC and LLVM/Clang.

The patches can be found on the GCC mailing list. These patches in turn will be found with GCC 15 that will see its stable release in the form of GCC 15.1 around March~April, well ahead of Xeon Diamond Rapids processors shipping and allowing time for this major compiler update to be packaged up by various Linux distribution vendors.