ChipStar 1.2 Released For Compiling & Running HIP/CUDA On SPIR-V/OpenCL Hardware
ChipStar 1.2 has been released as the open-source software enabling HIP/CUDA programs to be compiled and run atop SPIR-V whether it be OpenCL or Vulkan drivers.
ChipStar 1.2 is the newest version of this tooling for getting HIP/CUDA codes compiled and running on the SPIR-V IR with OpenCL and/or oneAPI Level Zero APIs. With running atop SPIR-V this allows supporting a variety of devices with either OpenCL or Vulkan drivers from different vendors. ChipStar 1.1 was already capable of running "various large HPC applications" while with ChipStar 1.2 there are yet more improvements.
ChipStar 1.2 introduces "cucc" as a drop-in replacement for the NVIDIA "nvcc" compiler. There is also enhanced OpenCL back-end support with supporting OpenCL's buffer device address extensive, optimized queue profiling, and performance optimizations.
For the Intel oneAPI Level Zero back-end there are various out-of-memory error fixes, improved thread safety, and other fixes. On the AMD HIP side is support for HIP 6.x as part of ROCm 6. Plus ROCm's hipBLAS, hipFFT, and rocRAND are now supported too.
The ChipStar 1.2 release page sums up this new version as:
Downloads and more details on ChipStar 1.2 via the GitHub release page
ChipStar 1.2 is the newest version of this tooling for getting HIP/CUDA codes compiled and running on the SPIR-V IR with OpenCL and/or oneAPI Level Zero APIs. With running atop SPIR-V this allows supporting a variety of devices with either OpenCL or Vulkan drivers from different vendors. ChipStar 1.1 was already capable of running "various large HPC applications" while with ChipStar 1.2 there are yet more improvements.
ChipStar 1.2 introduces "cucc" as a drop-in replacement for the NVIDIA "nvcc" compiler. There is also enhanced OpenCL back-end support with supporting OpenCL's buffer device address extensive, optimized queue profiling, and performance optimizations.
For the Intel oneAPI Level Zero back-end there are various out-of-memory error fixes, improved thread safety, and other fixes. On the AMD HIP side is support for HIP 6.x as part of ROCm 6. Plus ROCm's hipBLAS, hipFFT, and rocRAND are now supported too.
The ChipStar 1.2 release page sums up this new version as:
"This release brings significant stability and performance improvements, enhanced support for CUDA, new HIP/ROCm library ports and integrations for HipBLAS, HipFFT, HipRAND/RocRAND. Initial testing of running HIP/CUDA applications on RISC-V."
Downloads and more details on ChipStar 1.2 via the GitHub release page
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