More AMD "Glinda" SoC Enablement Code Begins Landing In Coreboot

Earlier this month I wrote about AMD "Morgana" and "Glinda" SoCs appearing in Coreboot for this open-source system firmware implementation. These are codenames we haven't seen talked about previously by AMD and this week more of the AMD Glinda SoC code has been published and merged into Coreboot.

Earlier this month the patches published were mostly focused on AMD Morgana but contained some AMD Glinda references too. Glinda is now catching up with getting more of the enablement code merged. We aren't positive what products Morgana and Glinda will map to with it not matching AMD's conventional product codenames on various roadmaps. Morgana and Glinda are more than likely Coreboot-minded codenames similar to AMD's Mendocino having used the "Sabrina" codename during its early development work in Coreboot prior to AMD announcing the Mendocino name.

But as it's Google engineers working with AMD on the Glinda and Morgana enablement, these SoC families are more than likely going to be used at least in part for various Google Chromebooks. On the consumer side Google Chromebook requirements continue to be one of the major drivers for having open-source Coreboot support.

Merged yesterday was 5.4k lines of new code adding the initial framework for the Glinda SoC. This big code drop is also building off of what was already published for Morgana.

Somewhat surprisingly for these new platforms is a few Family 17h references with Glinda. So like Mendocino it looks like this may be yet another take on Zen 2. We'll see with time if this ends up being some interesting budget AMD SoCs following Mendocino or simply an extension of that family.

In addition to that 5k lines of Glinda enablement code, merged overnight were also a bunch of Glinda blobs around the binary-only Platform Security Processor (PSP) support needed for Coreboot as well as the video BIOS binary.