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I would like to agree with you. But the problem with that line of thinking is that at this point in time, if you want a UI toolkit to support more than...Last edited by HadrienG; 25 November 2020, 04:35 AM.
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Can you expand a bit on your use cases ? I am asking because I used to have a somewhat similar problem (Windows/Linux/macOS file sync), but over recent...Last edited by HadrienG; 31 October 2020, 04:47 AM.
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I reached the same conclusion at the time. But since we had that pattern in multiple areas of the codebase, and I was worried about enforcing use of the...Last edited by HadrienG; 21 October 2020, 04:19 AM.
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I would beg to differ with even that assertion. In my experience, C++ tends to be harder to use correctly than Rust because it has a lot more edge cases,...Last edited by HadrienG; 20 October 2020, 04:31 PM.
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This is not about nullness, it is about non-null pointer/references pointing to a live or dead allocation.
From memory, the only form of...Last edited by HadrienG; 20 October 2020, 03:32 PM.
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I agree. As far as I see it, that's the main argument in favor of rewriting large bunches of existing infrastructure, as opposed to just writing new library...Last edited by HadrienG; 20 October 2020, 03:38 PM.
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Replying as someone who uses C++ daily at work and has spent way too much time getting comfortable with the intricacies of the recent standards for my...Last edited by HadrienG; 20 October 2020, 02:40 PM.
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This is false.
For a simple counter-example, iterator invalidation is a very common C++ memory safety bug, that no amount of modern C++ magic...Last edited by HadrienG; 20 October 2020, 02:28 PM.
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Yeah, with nanosecond timestamps, even at 64-bit, that's about what you get.
(Quick check : (2^64 nanoseconds / (about 10^9*3600*24*365.25...Last edited by HadrienG; 15 October 2020, 01:31 AM.
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No matter what you think about the choice of programming language, it's good to see AMD hiring some extra software devs. When comparing with the NVidia...Last edited by HadrienG; 25 September 2020, 12:45 AM.
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AFAIK most Xeon (server/workstation-marketed) chips don't have built-in graphics, and on the AMD side, since the Ryzen architecture, built-in graphics...
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It's been a while since I looked at it, but IIRC the currently proposed RISC-V vectorization model uses Cray vectors. Still SIMD-style execution under...
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And to make matters worse, here you are implicitly treating AVX-512 as a unified ISA extension like AVX-2. It is not. There is a myriad of "AVX-512"...
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