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RISC-V Backend Proposed For LLVM

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  • #1

    RISC-V Backend Proposed For LLVM

    Phoronix: RISC-V Backend Proposed For LLVM

    Open-source activities around the completely open RISC-V instruction set architecture sure are heating up. Alex Bradbury is proposing now that the RISC-V compiler backend be merged in LLVM...

    RISC-V Backend Proposed For LLVM - Phoronix
    http://www.phoronix.com/scan.php?page=news_item&px=RISC-V-LLVM-Backend
    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite
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  • #2
    I'm glad it's gotten to the point where they can look to merge it. They were talking about this at the workshop last month, somebody in there was looking to compile Rust on RISC-V.

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    • #3
      GCC has been *inarguably* leading with RISC-V ... how can you argue about who is leading if there is only one in the race....
      • Likes 1

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      • #4
        Originally posted by cb88 View Post
        GCC has been *inarguably* leading with RISC-V ... how can you argue about who is leading if there is only one in the race....
        Yeah, I'm hoping to see them upstream that as well; though there seems to be less pressure to do so. Also very excited to see people porting the other big compilers like v8 and JVM.

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        • #5
          Originally posted by microcode View Post
          Yeah, I'm hoping to see them upstream that as well; though there seems to be less pressure to do so. Also very excited to see people porting the other big compilers like v8 and JVM.
          Being Google and Oracle (v8 and JVM respectively) on the bandwagon as Platinum founding members... yeah it makes sense.

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          • #6
            A completely free and open ISA would ve great... if only we could see real high end CPUs implementing it one day, not just mobile SoCs.

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            • #7
              Originally posted by jacob View Post
              A completely free and open ISA would ve great... if only we could see real high end CPUs implementing it one day, not just mobile SoCs.
              The indian government is making HPC, workstation, and server parts with RISC-V right now; they seem to be throwing tens of millions of dollars at it already.

              I don't think there's a question as to whether or not there will be high-performance RISC-V parts, but when.

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              • #8
                Originally posted by microcode View Post

                The indian government is making HPC, workstation, and server parts with RISC-V right now; they seem to be throwing tens of millions of dollars at it already.

                I don't think there's a question as to whether or not there will be high-performance RISC-V parts, but when.
                Intel probably spends more than that on a set of masks... at 14nm not including any of the additional development costs.

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